Analog Mixed Signal Design Engineer

Intel Corporation • Ottawa, ON

1d • Hybrid

About The Position

Join Intel's cutting-edge mixed-signal IP development team as a Senior Mixed Signal Design Engineer. This role combines analog circuit design expertise with specialized focus on static timing analysis for next-generation mixed-signal systems. You'll drive timing closure across analog-digital interfaces while supporting comprehensive design verification activities that directly impact Intel's industry-leading products. Working in a collaborative environment with analog designers and system architects, you'll leverage tools like Cadence ADE to execute simulations, debug complex testbenches, and optimize circuit performance. This position offers significant opportunities to enhance verification methodologies and contribute to behavioral modeling initiatives that accelerate silicon success. If you are passionate about analog circuit design combined with mixed-signal verification (especially static timing analysis), and you thrive in a fast-paced, collaborative setting, we encourage you to apply.

Requirements

• Bachelor's degree in Electrical or Computer Engineering or in a STEM related field with 2+ years of industry experience
• 2+ years of experience with mixed signal verification and driving methodology changes and initiatives.
• 2+ years of experience in scripting languages such as Python for automation purposes.
• Strong analytical and problem-solving skills, alongside effective team collaboration capabilities.
• Good communication skills

Nice To Haves

• Post Graduate degree in Electrical or Computer Engineering or in a STEM related field.
• Experience working within mixed signal systems like SerDes or PLLs.
• Experience with static timing analysis and analog circuit designs.
• Experience with Cadence ADE for running simulations and debugging testbenches.
• Experience with script development and automation using AI.
• Experience with mixed-signal design principles, including interfaces between analog and digital domains.
• Experience with analog behavioral modeling (Verilog-A, SystemVerilog, etc.) is a plus

Responsibilities

• Lead static timing analysis (STA) execution for mixed-signal designs, ensuring robust timing closure across analog-digital interfaces
• Drive timing optimization and constraint development for complex mixed-signal systems
• Execute analog circuit design tasks including simulation setup, testbench development, and schematic optimization using Cadence ADE
• Perform comprehensive mixed-signal verification encompassing analog simulations, behavioral modeling, and timing analysis
• Analyze simulation results for power, performance, and reliability compliance
• Investigate and resolve complex issues in analog testbenches and mixed-signal simulations
• Root-cause analysis of pre-silicon design challenges with systematic corrective action implementation
• Collaborate across disciplines with analog designers, digital architects, RTL teams, and physical design engineers
• Develop behavioral models to improve simulation accuracy and efficiency
• Advance verification flows and methodologies supporting evolving mixed-signal design requirements
• Contribute to automation initiatives using scripting and emerging AI technologies

Benefits

• Intel provides accommodations to applicants and employees with disabilities.
• Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
• We do not charge any fees during our hiring process.
• Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior