Analog Designer (1 year contract)

Advanced Micro Devices, Inc•Markham, ON

About The Position

The I/O Pad Ring Team is looking for a candidate to perform I/O pad ring physical verification duties and methodology improvements on multiple exciting AMD products being created today. I/O Pad Ring refers to the input/output interfaces that are loosely found in a ring around the chip. Interfaces like PLL (phase lock loop), DDR, GDDR, USB, HDMI, PCIE, GPIO all reside in the IO Pad Ring. SOC level verification takes many days now. The IO Pad Ring function takes a subset of analog IPs to pre-verify them in order to pre-fetch any issues prior to final integration. This team is essential to the success of AMD as a cutting edge company. You will be working on some of the most exciting projects the industry has to offer. CPU/ GPU / APU and semi-custom AMD's products featured in Sony Playstation and Microsoft Xbox, to name a few. It is a very exciting environment and you will be working with the very best in our technology.

Requirements

Strong understanding of physical verification checks (Layout VS Schematic /Design Rule Check /Electronic Rule Check/PERC), and ability to debug and resolve issues.
Knowledge of chip level integration and Electrical Static Discharge /LUP concepts.
Must have ability to communicate with various teams to articulate issues, requirements as they pertain to layout in order to facilitate solutions
Physical verification experience using Mentor Calibre (Laoyt VS Schematic, Design Rule Check, PERC), and Synopsys tools (ICC/ICC2/ICV).
Must be able to work independently and as part of a team
Electrical/Computer/Biomedical/Mechanical Engineering Degree and/or Electronics related Diploma

Nice To Haves

Experience doing physical verification for tile of chip physical design would be an asset.
Perl programming, TCL, SVRF, TVF programming not required, but would be advantages
IP layout design experience and exposure to Cadence is a plus.

Responsibilities

Assembly of macros/IPs/RDL into an I/O pad ring database, and then running various verification tools on that assembled database to determine integration issues.
Communication with various IP owners may be required to facilitate issue resolution.
Construction of product I/O pad rings using established flows and scripts.
Physical verification on designs that contain up to 200M devices including: LVS, DRC, ERC and PERC.
Delivery of all needed waivers(Electronic Rule Check /Design Rule Check /EDRC/PERC) and documentation to SoC teams
Facilitate ESD and design reviews for 3rd party IPs and I/O ring
Tracking of IP versions, visual inspections and in-context XOR verifications.