Analog Design Engineer

OMNIVISION•Santa Clara, CA

1d•$156,853 - $160,000

About The Position

The Analog Design Engineer will be responsible for the design and development of image sensor technologies. This includes transistor-level design of analog and mixed-signal circuits for CMOS Image Sensors, such as pixel arrays, column amplifiers, switched capacitors, comparators, ramp generators, ASRAM, and XDEC using Cadence Virtuoso. The role also involves whole chip floorplan design, pad frame design, and analog/mixed-signal circuit layout design using Cadence Virtuoso. Collaboration with layout engineers for chip layout integration and improvement, and performing simulations for sub-blocks and the entire image sensor readout circuit using simulators like Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice are key aspects. Design verification, including DRC, LVS, and PERC checks using Siemens Caliber, is also required. The engineer will collaborate with Digital Engineers to define and design analog-to-digital interfaces and work with verification, process, test, and application engineers to debug, characterize, and optimize fabricated image sensors. The position requires proposing innovative solutions, conducting new circuit R&D, and staying ahead of current technology. Processing column readout data from CMOS sensors using software like Excel and MATLAB, performing performance checks, and conducting debug analysis are also part of the responsibilities. Additionally, the role involves designing internal discrete-time circuits, peripheral circuits, and timing control for CMOS image sensors, including bias circuits, driver/level shifters, switched capacitors, logic gates, and slew rate control.

Requirements

Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineer, Electro-Optics, or a related field with graduate level course work of Analog IC Design, Data Converters, and VLSI Circuits and Technology.
Layout design and floor planning.
Testing and troubleshooting power IC.
Using lab equipment testing specific IC.
Photonic device manufacturing processes and principles, e.g. SPAD, CMOS sensors, Optical filters.
Matlab and Excel to do signal processing, imaging processing and data analysis.
Feedback, opamp, switched-capacitor circuits, layout and mismatch, and noise.
Data converter systems and circuits, including ADC and DAC architecture such as flash, two-step, pipelined, algorithmic, successive-approximation, R-2R DACs.
Analysis and design of modern digital circuits.
Design and analyze CMOS digital circuit.
Use commercial software Cadence.

Responsibilities

Conduct design and development of image sensor technologies.
Work on transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso.
Work on whole chip floorplan design and pad frame.
Work on analog and mixed signal circuits layout design by Cadence Virtuoso, such as column_array.
Collaborate with layout engineer on whole chip layout integration and improvement by Cadence Virtuoso.
Perform sub-blocks and whole image sensor readout circuit simulation by simulators such as Analog FastSPICE (AFS), Empyrean ALPS and NanoSpice.
Perform design verification such as DRC, LVS, PERC check by using Siemens Caliber.
Collaborate with Digital Engineer to define and design the analog to digital interface.
Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors.
Propose innovative and creative solutions along with new circuit R&D and be ahead of current technology.
Process the column readout data from the CMOS sensor using data processing software like Excel and MATLAB.
Perform a performance check and conduct debug analysis based on the data results.
Design the internal Discrete-time Circuits, Peripheral circuits and Timing control for a CMOS image sensor, including bias circuits, driver/level shifter, switched capacitor, logic gates and slew rate control.