AI SoC Hardware Architect

Ericsson•Austin, TX

1d•Onsite

About The Position

The Architect Who Closes the Gap. The Engineer Who Makes Silicon Inevitable. Location: Austin, TX Team: Cross-functional leadership across Model Engineering, AI Infrastructure, and Silicon Architecture The Problem Nobody Else Is Solving Most chip programs are full of brilliant people who never quite speak the same language. Researchers build ambitious AI models. Silicon teams build powerful hardware. Infrastructure teams wire it all together. And somewhere in the space between those three worlds — in the handoffs, the assumption gaps, the untranslated requirements — massive performance dies quietly on the floor. We're not hiring someone to manage that problem. We're hiring the person who architects it out of existence. The Role As Principal AI Hardware Architect, you will own the most consequential technical contract in the company: the binding agreement between what AI workloads demand, what software systems can express, and what custom silicon can physically deliver. This is not a support role. This is not a liaison role. This is the highest-leverage engineering seat in the building — the person who looks at a next-generation LLM, a multimodal inference pipeline, or a signal processing workload and answers the question that determines whether a chip program succeeds or settles: "Here's exactly what this workload needs from silicon — and here's the proof it will work before we ever tape out." Your decisions won't live in documents. They'll be etched into hardware. Your performance models will guide compute investments. Your architectural direction will shape memory hierarchies. Your cross-team alignment will determine whether the company builds capable hardware — or hardware nobody else can touch.

Requirements

AI/ML Systems Depth: You understand modern AI architectures from the inside — inference systems, quantization strategies, deployment constraints, and how workload behavior actually manifests in silicon utilization. You don't just know what a Transformer does. You know what it costs.
Silicon Architecture Fluency: You've worked with processor, accelerator, or custom silicon architectures. Compute pipelines, memory hierarchies, on-chip interconnects, performance tradeoff analysis — this is native territory for you, not background reading.
12+ years of industry experience across AI, systems, or silicon
Proven experience at the intersection of hardware and intelligent compute systems
Hardware/software co-design leadership across full product cycles
Demonstrated performance modeling expertise — analytical, simulation, or cycle-approximate
Track record of influencing architectural and product decisions across multiple technical organizations
Exceptional written communication and technical specification ability
Strong Python and C++ skills

Nice To Haves

Experience with custom silicon, accelerators, or advanced hardware platforms
Prior involvement in ISA definition, memory hierarchy design, or accelerator roadmap decisions

Responsibilities

Analyze workload specific testcases tailored to real-world applications, using LLMs, multimodal systems, signal processing pipelines, inference engines - and translate them into the concrete hardware requirements that can be implemented.
You are the bridge that doesn't bend. You connect model engineering, AI infrastructure, and silicon architecture teams so that every major hardware investment is both architecturally sound and software-accessible. When workload ambition outpaces hardware capability, you find the path forward. When silicon innovation creates a performance unlock, you make sure the software stack can actually reach it.
Performance Modeling Ownership: Before a single gate is placed, your analytical, simulation, and cycle-approximate performance models are already shaping the architecture. You build and create the performance modeling environment that determine compute investments, memory hierarchy decisions, and feature prioritization — turning uncertainty into defensible, data-driven direction.
Real Workload Validation: You profile real workloads on real and future platforms. You find the bottlenecks — in memory, compute, scheduling, and architecture — and you feed those findings directly into the next hardware and software cycle. No guesswork. No assumptions. Just ground truth.
Strategic Technical Translation: You align people who think in different languages. Hardware architects, AI researchers, and infrastructure teams all operate with different mental models and different vocabularies. You translate across all of them — grounding every product decision in real workloads, measurable constraints, and practical execution paths.

Benefits

Choice of three medical plan options
Dental plan option
Company credits towards medical and dental premiums
The Ericsson US 401(k) Plan offers an automatic 3% company contribution
Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
Company credits towards basic life insurance and basic accidental death and dismemberment coverage
Company credits towards short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave at 100% of pay
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs