AI SoC Architect Networking

Majestic Labs • Los Altos, CA

3d

About The Position

This is a highly technical and cross-functional role requiring deep expertise in SoC networking, high-speed interconnects, and protocol acceleration for AI. As a SOC System Network Architect for AI, you will lead the definition and architectural design of network engines and interconnect fabrics powering our custom AI servers. You will collaborate closely with silicon architecture, hardware design, firmware, and software teams to shape scale-up and scale-out networking topologies optimized for distributed AI workloads.

Requirements

• 7+ years of hands-on network architecture, SoC interconnect design, or silicon engineering experience, with at least 3 years in an architecture or technical lead capacity
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science
• Proven track record of owning and delivering complex network ASICs, NIC engines, or switch architectures from initial concept through silicon bring-up
• Deep expertise in SmartNIC/NIC architecture, RDMA technologies (RoCEv2, InfiniBand), and hardware transport protocol engines
• Strong understanding of scale-up and scale-out topologies, high-speed packet processing, and switch architecture trade-offs
• In-depth knowledge of AI communication patterns and hardware acceleration for network collective operations
• Solid foundation in lower-level network protocols (TCP/UDP, Ethernet, IP) and advanced network congestion control mechanisms
• Proficiency in network performance modeling, hardware simulation tools, and architectural trade-off analysis

Nice To Haves

• Experience with high-speed proprietary interconnects (e.g., NVLink, NVSwitch, UALink, CXL) or custom switch silicon
• Hands-on experience with network simulation and modeling frameworks (e.g., ns-3, OMNeT++, SystemC/TLM)
• Familiarity with distributed AI communication libraries (e.g., NCCL, RCCL) and frameworks (PyTorch, DeepSpeed)

Responsibilities

• Architect end-to-end SoC networking engines, SmartNIC/NIC architectures, and switch interface IPs for AI accelerators
• Define scale-up (intra-node) and scale-out (inter-node) network topologies
• Design hardware acceleration and offload engines for AI collective operations (e.g., AllReduce, AllGather, AllToAll) directly on the network fabric
• Optimize transport protocols (RoCEv2, custom RDMA engines, TCP/UDP offloads) and adaptive routing/congestion control algorithms (e.g., DCQCN) for synchronized AI traffic flows
• Drive performance modeling, cycle-accurate simulations, and traffic pattern analysis to evaluate architectural trade-offs across network fabrics
• Collaborate with ASIC design, silicon architecture, and AI software teams to define hardware/software interfaces, register abstractions, and programming models
• Produce high-quality network architecture specifications, interface documents, and lead cross-functional architecture reviews

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree