3D Heterogeneous Integration Engineer (2026 New College Graduate)

GlobalFoundries•Malta, NY
•$65,400 - $145,800•Onsite

About The Position

GlobalFoundries Fab 8 is seeking a motivated integration engineer for its state-of-the-art 300mm fabrication facility in Malta, New York. The role drives new development to enable next-generation advanced packaging R&D efforts. The engineer leads through-silicon-via (TSV) process development and planning, collaborates with outsourced assembly and test providers on wafer-level integration processes, and develops expertise in relevant processes, materials, and tooling. The position also drives understanding of failure modes and develops integration schemes to improve yields, reduce cycle time and costs, generate intellectual property, and enable new capabilities, early product prototyping, and qualification across multiple programs.

Requirements

  • PhD with completed defended thesis, or a master's degree in Electrical Engineering, Materials Science, or a related field from an accredited degree program.
  • At least a 3.0 overall GPA and proven good academic standing.
  • English fluency, written and verbal.

Nice To Haves

  • Prior related internship or co-op experience in process engineering or integration.
  • Fundamental knowledge of semiconductor packaging processes.
  • Demonstrated leadership experience in the workplace, school projects, competitions, or similar settings.
  • Project management skills, including the ability to innovate, execute solutions, and navigate ambiguity.
  • Strong written and verbal communication skills.
  • Strong planning and organizational skills.

Responsibilities

  • Lead TSV process development efforts and planning in collaboration with unit process engineers, tools, and materials at the Malta Fab 8 advanced semiconductor fab.
  • Collaborate with outsourced assembly and test providers to develop new wafer-level integration processes.
  • Develop expertise in processes such as etch, lithography, plating, and CMP, as well as materials and tooling, using available characterization resources.
  • Drive mechanistic understanding of failure modes.
  • Develop integration schemes to continuously improve yields and reduce cycle time and costs.
  • Generate intellectual property related to novel wafer integration and packaging technology.
  • Drive end-to-end process integration and planning to enable new capability planning, early product prototyping, and qualification across multiple programs.
  • Perform activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs.
  • Perform other duties as assigned by the manager.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service