About The Position

As a Wireless Radio Verification Engineer, you'll verify Radio digital controllers combined with RF subsystems that enable exceptional wireless performance. You'll develop verification environments for complex radio control / transceiver paths spanning PLLs, DAC / ADC data paths, power management, and co-existence mechanisms. This role emphasizes digital verification while bridging to RF/analog domains—you'll work closely with Design, RF, PHY, and Systems teams to understand radio specifications and develop comprehensive test strategies. You'll own subsystem verification from test planning through coverage closure, building testbench components and scenarios that exercise complex radio control sequences and operating modes.

Requirements

  • Minimum requirement of a bachelor’s degree.
  • Understanding of ASIC verification flows with SystemVerilog including UVM testbench development, scenario creation, and RTL simulation.
  • Experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
  • Experience with digital design fundamentals Verilog or VHDL.
  • Experience with scripting languages such as Python, or similar.
  • Strong problem-solving abilities and collaborative approach to engineering challenges.

Nice To Haves

  • Experience with digital controllers, subsystems, or data paths.
  • Experience with constrained random testing, functional coverage implementation, UVM methodology, and assertion-based verification.
  • Exposure to mixed-signal modeling concepts including real-number modeling.
  • Exposure to RF/analog system design such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC / ADCs.
  • Proficiency with Python, Perl, Bash or similar scripting for automation.
  • Great teammate with excellent communication skills and desire to seek diverse technical challenges.
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