The Wafer Fab Process Technician is a production and technical lead responsible for running volume production and maintaining process stability, recipe control, and yield performance across InP photonic device lines, including InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips (GC). The role primarily operates PECVD dielectric deposition systems, ICP/RIE dry etch systems, and wet etch benches. Work includes dielectric masking, Mesa etch, and surface preparation supporting MOCVD epitaxial regrowth of InP current-blocking layers, as well as dielectric passivation of finished devices. The Technician works with minimal supervision in a III-V cleanroom environment to meet throughput targets, investigate process excursions, maintain Process-of-Record (POR) discipline, and mentor junior technicians and operators. The position operates PECVD systems to deposit SiO2 and SiNx films, ICP/RIE systems for dielectric patterning and InP/InGaAsP Mesa etch, and wet benches for stripe etch, BOE oxide removal, resist strip, and pre-regrowth surface cleans. It also involves chamber maintenance and qualification, lot prioritization, in-line metrology and inspection, process troubleshooting, SPC and recipe ownership, root-cause investigations, process qualifications, and training support. The role may require flexibility to support engineering runs or excursions outside standard shift hours. A reasonable estimated pay range is $25–$36. Base salary considerations include job-required qualifications, skills, education and experience, job location, and other elements of total compensation.
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Job Type
Full-time
Career Level
Mid Level
Education Level
Associate degree