VP of HW Systems Engineering

Axiado • San Jose, CA

9h • Onsite

About The Position

We are seeking an agile, results-driven VP of HW Systems Engineering to lead our hardware organization. In this highly visible role, you will own the hardware product lifecycle from concept to high-volume production for the Axiado Trusted Control/Compute Unit (TCU) products. This role requires an executive with elite, hands-on design and debugging capabilities who thrives in the lab and effectively navigates dynamic, supply-chain-constrained environments. You will manage senior engineers and contractors, help customers build secure server infrastructure, and champion open hardware ecosystems like the Open Compute Project (OCP).

Requirements

• 20+ years of hardware engineering experience with a leadership track record in server, data center, or semiconductor ecosystems.
• B.S. or M.S. in Electrical Engineering (EE).
• Proven history of taking complex board designs to high-volume production with excellent yields and resolving field RMA issues.
• Deep, continuous experience with circuit design, schematic capture, laboratory equipment, and platform troubleshooting.
• Strong knowledge of OCP DC-SCM standard solutions (DC-SCI interface, form factors) and a solid network across hyperscaler and OEM partners.
• Demonstrated capability to execute rapid hardware redesigns, footprint compatibility strategies, and alternative component sourcing.
• Expert familiarity with Cadence OrCAD/Allegro and server interfaces (PCIe, USB, I2C, SMBus, SPI, UART, USB, MCTP, eSPI, LTPI).
• Solid understanding of modern CPU/GPU architectures and the Linux environment (including Python or Bash scripting).
• Exceptional verbal and written communication skills to articulate hardware-anchored security and supply chain strategy to enterprise stakeholders.

Responsibilities

• Drive TCU-based embedded systems from initial concept through high-volume production with active, hands-on daily execution.
• Take complex boards to mass production while optimizing DFM/DFT, factory test coverage, and production yields.
• Oversee the technical resolution of customer field returns, driving Failure Analysis (FA) and corrective actions to improve reliability.
• Partner with cross-company ASIC, silicon, firmware, and software teams to systematically isolate and resolve complex system bugs.
• Personally lead first-silicon and platform bring-up, low-level bus validation, and EVT/DVT testing in the lab.
• Integrate OCP DC-SCM standards and represent the company within OCP and other industry hardware forums.
• Pivot board layouts responsively based on real-time parts availability and manage critical tier-1 supplier relationships.
• Drive schematic development in Cadence OrCAD and collaborate with Layout, Mechanical, and SI engineers to meet OCP DC-SCM and NVIDIA IFF form factors.

What This Job Offers

• Job Type: Full-time
• Career Level: Executive