VLSI CAD Engineer

Apple•Cupertino, CA

5d•$148,987 - $194,700•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Support and enhance the Apple synthesis flow by optimizing processes and resolving any CAD tool issues that arise during the synthesis of System-on-Chip (SoC) partitions; Work with industry-standard Electronic Design Automation (EDA) tools such as Cadence Genus and leveraging the Tel scripting language to fine-tune the synthesis flow, ensuring efficient and robust design implementation; Engage in a proactive approach to troubleshooting, debugging, and refining synthesis methodologies to maintain seamless functionality within the Apple silicon design framework; Validate and improving features that contribute to Power, Performance, and Area (PPA) enhancements; Collaborate with the vendor team to refine and optimize these features, aligning them with the unique requirements of Apple silicon; Perform an in-depth analysis of how each feature impacts PPA metrics, allowing for the identification of optimization opportunities; Perform continuous monitoring and evaluation of the effectiveness of these enhancements, which help ensure that Apple's synthesis and design methodologies remain efficient and tailored to the evolving needs of high-performance SoC designs; Conduct Synthesis and Place-and-Route (PnR) experiments on various SoC partitions to assess and validate new design features before incorporating them into production workflows; Leverage a strong understanding of Register Transfer Level (RTL) design and an analytical approach to evaluating the effects of different plugins and attributes on design metrics; Extend synthesis experiments through the PnR stage, which ensures that the correlation of Power, Performance, and Area (PPA) remains consistent across different design phases; Ensure the post-synthesis and post-PnR results are well-aligned, which leads to an accurate and efficient implementation in final production-ready designs; Collaborate with cross-functional teams, such as the Logic Equivalence (LEQ) team, to validate new features after synthesis; Ensure the synthesized design maintains logical equivalence with the original RTL; Develop automation scripts using Python to further streamline the synthesis workflow, which significantly reduces manual intervention and improves overall productivity. 40 hours/week.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering or related field
Using synthesis EDA tool, EDA tool optimization, and CAD tool troubleshooting to achieve timing closure, resolve quality-of-results issues, and improve design convergence across multiple process nodes
Utilizing scripting languages for synthesis flow automation, including fine-tuning design implementation workflows
Using scripting tools for automation development, including creating utilities and streamlining synthesis workflows
Experience with System-on-Chip (SoC) methodology, Place-and-Route (PnR) experimentation, and validation of design features to verify physical implementation feasibility, ensure design integrity, and optimize floor planning strategies
Using Register Transfer Level (RTL) design analysis to evaluate design metrics and correlation analysis
Utilizing Power, Performance, and Area (PPA) optimization, feature validation, and enhancing automation flows to meet product specifications, reduce power consumption, and maximize performance within area constraints
Using Logic Equivalence Checking (LEC) validation methods and cross-functional collaboration for design verification
Using post-synthesis and post-PnR correlation analysis to ensure accuracy in production-ready designs
Utilizing synthesis methodology development and refinement for proactive troubleshooting and debugging approach

Nice To Haves

Responsibilities

Support and enhance the Apple synthesis flow by optimizing processes and resolving any CAD tool issues that arise during the synthesis of System-on-Chip (SoC) partitions
Work with industry-standard Electronic Design Automation (EDA) tools such as Cadence Genus and leveraging the Tel scripting language to fine-tune the synthesis flow, ensuring efficient and robust design implementation
Engage in a proactive approach to troubleshooting, debugging, and refining synthesis methodologies to maintain seamless functionality within the Apple silicon design framework
Validate and improving features that contribute to Power, Performance, and Area (PPA) enhancements
Collaborate with the vendor team to refine and optimize these features, aligning them with the unique requirements of Apple silicon
Perform an in-depth analysis of how each feature impacts PPA metrics, allowing for the identification of optimization opportunities
Perform continuous monitoring and evaluation of the effectiveness of these enhancements, which help ensure that Apple's synthesis and design methodologies remain efficient and tailored to the evolving needs of high-performance SoC designs
Conduct Synthesis and Place-and-Route (PnR) experiments on various SoC partitions to assess and validate new design features before incorporating them into production workflows
Leverage a strong understanding of Register Transfer Level (RTL) design and an analytical approach to evaluating the effects of different plugins and attributes on design metrics
Extend synthesis experiments through the PnR stage, which ensures that the correlation of Power, Performance, and Area (PPA) remains consistent across different design phases
Ensure the post-synthesis and post-PnR results are well-aligned, which leads to an accurate and efficient implementation in final production-ready designs
Collaborate with cross-functional teams, such as the Logic Equivalence (LEQ) team, to validate new features after synthesis
Ensure the synthesized design maintains logical equivalence with the original RTL
Develop automation scripts using Python to further streamline the synthesis workflow, which significantly reduces manual intervention and improves overall productivity