Verification Engineer, Senior

Qualcomm • Toronto, ON

5d • CA$104,900 - CA$154,900

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
We are looking for experienced SoC design verification engineers to contribute to our next generation connectivity networking products. This is an incredible opportunity to be part of the AI revolution and contribute to the complete semiconductor development cycle, from concept to product.
The ideal candidate will have a strong and extensive background in RTL verification methodologies, UVM, C and SystemVerilog. You will be responsible for driving pre-silicon verification, collaborating with cross-functional teams, and ensuring the successful validation of high-performance SoCs.

Requirements

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Multi-year experience in Design SoC Verification
• An applied understanding of UVM and verification techniques
• Experience with constrained-random verification in System Verilog and UVM
• Formal Verification, and Power-aware UPF verification techniques
• Tools/Languages - System Verilog, UVM, Python, Perl, C/C++
• Post-Silicon Debug: Experience in post-silicon bring-up and debugging.
• Communication & Leadership: Team player with strong communication skills to ensure effective program execution.

Nice To Haves

• Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
• Knowledge in Ethernet and PCIe standards is desirable

Responsibilities

• Build testbenches and analyze test failures to uncover bugs in IP
• Integrate 3rd party VIPs for compliance testing of standard protocols
• Build releases of our design into SoC design integration team
• Take on opportunities to lead, plan, and coordinate tasks with team members
• Collaborate closely with IP design, FE design, PD , PV,EM/IR and post-si teams
• Contribute towards the continuous improvement of IP verification methodologies and processes

Benefits

• Competitive compensation and career growth opportunities.
• competitive annual discretionary bonus program
• opportunity for annual RSU grants
• highly competitive benefits package is designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior