Verification Engineer Senior

Intel Corporation•Austin, TX

1d•$190,610 - $269,100•Hybrid

About The Position

Intel is seeking a highly qualified candidate to join our ASIC design verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting-edge, customer impacting technology development. We embrace innovative and efficient methodologies that drive at-scale product execution. Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis. Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career-defining achievements. If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 8+ years of experience in ASIC/FPGA design verification, or a Master’s degree with 6+ years of experience in ASIC/FPGA design verification
Object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
Developing UVM and/or Formal based verification architectures and methodologies.
Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and Low-speed communication protocols (UART, SPI, I2C/I3C))
Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills.

Nice To Haves

Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience.
Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
Experience with scripting languages.

Responsibilities

Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and confirm to microarchitecture specifications.
Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs. Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies. Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.