Verification Engineer, Emulation and Prototyping

NVIDIA•Santa Clara, CA

5d•$136,000 - $264,500•Onsite

About The Position

We are looking for hardworking systems engineers who will craft DV/Verification knowledge and extend to emulation & FPGA environments for our next generation GPUs, SOCs, NICs, and Switches on industry-standard FPGA prototyping and emulation platforms. We are now looking for a Verification Engineer, Emulation & Prototyping to join our team onsite in Santa Clara, CA.

Requirements

BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 5+ years of experience, or MS with 3+ years of proven experience in FPGA prototyping and/or hardware emulation.
Strong understanding of FPGA prototyping and hardware emulation architectures, devices, flows, and tools.
Hands-on experience with Simulators or Emulators across vendors
Hands-on experience with emulation platforms such as Synopsys ZeBu, Siemens Veloce Synopsys or Cadence Z3.
Familiarity with ProtoCompiler or Synplify Premier, Xilinx Vivado,
Extensive knowledge of writing SV/Verilog code for TB-Emulator , high speed integrations
Understanding of industry-standard protocols such as PCIe, CXL, NVLINK, USB, CHI, and CPU-GPU coherency.
Candidates must have strong expertise in crafting and optimizing emulation-friendly C/C++ testbenches and transactors. These must function efficiently at emulation speeds.
Experience minimizing host-emulator communication bottlenecks and improving transaction efficiency is necessary.
Additionally, crafting scalable validation environments based on software for high-performance SoCs and multi-ASIC systems is required.
Ability to develop efficient DPI/PLI/SystemC-based interfaces and software infrastructures that enable high-speed validation, debug, and bring-up on hardware emulation platforms.

Nice To Haves

Ability to actively code in C/C++ , Python and perl
Use agentic, Claude to improve coding or drafting solutions for a problem
Prior experience with hardware emulation or prototyping platforms (Synopsys HAPS, ZeBu, Siemens Veloce) of a high-performance processor or SOC is highly desirable.
Understanding of performance-sensitive validation methodologies for large-scale emulation environments, including efficient logging, synchronization, memory handling, and protocol traffic generation and experience enabling pre-silicon software validation, firmware bring-up, or system-level debug on emulation platforms is a plus!
Understanding of Cadence/Synopsys/Siemens transactor solutions.

Responsibilities

Build emulation and FPGA environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows.
Improve performance of emulation and FPGA platforms, analyze timing/performance bottlenecks, and generate bitstreams/images.
Bring new DV Test benches that can provide high-level abstraction of C/SV TB, running at FPGA speeds.
Bring up designs on hardware emulation & FPGA platforms and drive complex debug and problem-solving activities.
Scale emulation/FPGA verification methodology in order to cater extensive test-plans
Work closely with architects, designers, verification engineers, validation teams, and software teams to accomplish project goals.
Enable pre-silicon software development, validation, and performance analysis using hardware emulation & FPGA environments.
Develop and optimize emulation-friendly validation infrastructures, including high-performance software interfaces and scalable debug methodologies.