UIUC Research Park Intern - Hardware Functional Safety

Rivian•Champaign, IL

About The Position

Rivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2028 through May 2028. Rivian's Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities. Rivian is an equal opportunity employer and does not use graduation dates to determine the age of applicants or as a basis for discriminatory hiring decisions. If you are not pursuing a degree, please see our full time positions on our Rivian careers site. Note that if your university has specific requirements for internship programs, it is your responsibility to fulfill those requirements. We are looking for a detail-oriented Hardware Functional Safety Engineer to join our engineering team. In this role, you will be at the front lines of ensuring our next-generation safety-critical systems—specifically High-Performance SoCs and complex PCBs—are robust enough to handle the rigors of real-world deployment. You will focus on identifying potential failure points through rigorous systematic analysis, ensuring that our hardware designs are resilient against both random hardware failures and common-cause dependencies.

Requirements

Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign
Actively pursuing a degree or one closely related in Electrical Engineering or Computer Engineering
Foundational knowledge of ISO 26262 (specifically Parts 5, 9, and 11)
Understanding of FTA (Qualitative/Quantitative) and the principles of DFA
Ability to read and interpret PCB schematics and understand SoC internal blocks (CPUs, Interconnects, Memory)
A "safety-first" mindset, extreme attention to detail, and the ability to explain complex failure modes to design engineers.

Nice To Haves

Experience with safety analysis tools (e.g., Ansys medini analyze, Item Toolkit, or Reliability Workbench)
Knowledge of ASIL (Automotive Safety Integrity Level) decomposition strategies
Familiarity with hardware description languages (Verilog/VHDL) or hardware verification.
Practical experience with physical layout constraints that impact DFA (e.g., substrate isolation, power domain separation)

Responsibilities

Supporting the functional safety lifecycle for hardware components through quantitative and qualitative analysis.
Support top-down FTA (Fault Tree Analysis) to identify combinations of hardware failures that could lead to a violation of safety goals.
Help build logic trees to visualize and quantify the probability of catastrophic system failures.
Conduct DFA (Dependent Failure Analysis) to identify potential "freedom from interference" issues.
Analyze shared resources (e.g., clock trees, power rails, or physical proximity on a PCB) to identify Cascading Failures and Common Cause Failures (CCF) that could bypass safety redundancies.
Assist in performing quantitative FMEDA (Failure Modes, Effects, and Diagnostic Analysis) to calculate hardware architectural metrics (SPFM, LFM) and the Probabilistic Metric for random Hardware Failures (PMHF).
Evaluate the effectiveness of safety mechanisms in detecting or controlling hardware faults.
Review hardware requirements and schematics to ensure safety mechanisms (e.g., ECC, parity, redundant paths, voltage monitors) are correctly implemented to mitigate the faults identified in your FTA and DFA.
Contribute to the creation of Work Products required by ISO 26262, such as the Hardware Safety Analysis Report and Safety Case fragments.