Toolchain / Digital Design Engineer

Southeastern Cyber•Lincolnton, GA

5d•Remote

About The Position

Southeastern Cyber LLC is seeking a Digital Design / Toolchain Engineer to extend our proprietary toolchains and pipelines. The engineer will integrate various policies into an automated flow for system and hardware design. We are a Service-Disabled Veteran Owned Small Business (SDVOSB) based in Lincolnton, Georgia. We are a hardware security and AI silicon product company building the systems that the nation depends on — from weapon platforms to critical infrastructure. Our mission is to deliver hardware-rooted security and deterministic AI inference capabilities that survive full-stack compromises and operate reliably in the most demanding environments. Our applied engineering and product development efforts are supported by and aligned with key federal and academic partners. We actively engage with: NVIDIA Inception: Member of NVIDIA's program supporting startups advancing AI and accelerated computing Federal Partners: Critical DoD programs and federal research agencies Academic Research: Leading academic institutions specializing in hardware security. Every system we build follows the same engineering philosophy: express everything as code, automate everything that can be automated, and bake security in from the architecture level rather than treating it as a software layer after the fact. Hardware validation, verifiable deployments, and immutable logic gates — these aren't buzzwords for us, they're how we actually ship systems. Every project carries full integration for rigorous testing, secure manufacturing, and trusted execution.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
Demonstrated expertise in EDA toolchains, RTL design (Verilog/SystemVerilog/VHDL), and digital logic synthesis.
Strong scripting and automation skills for EDA flows.
US Person (Citizen or Permanent Resident) eligible to work on defense-related technology.

Responsibilities

Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or Rust).
Map quantified requirements into physical standard-cell routing and logic structures.
Run synthesis, place-and-route, and area/power/timing (PPA) estimates to sweep architectural scaling limits (max model parameter count, max whitelist/blacklist size).
Interface with the Principal Investigator and Hardware SME to ensure correct RTL generation and physical implementation.