Timing Engineer

Altera Semiconductor • San Jose, CA

19h • Onsite

About The Position

Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will lead timing activities for a subsystem, partnering closely with the Design, Architecture, and Physical Design teams to achieve timing convergence from implementation through final sign-off. The ideal candidate brings strong expertise in static timing analysis (STA), timing constraints, and timing closure methodologies, with experience working on advanced process technologies. You will play a key role in driving subsystem timing closure, developing timing methodologies, and collaborating across engineering teams to deliver high-quality FPGA products.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 5+ years of experience in ASIC or FPGA timing analysis and sign-off.
• 5+ years of experience in timing analysis, static timing analysis (STA), and timing sign-off.
• 5+ years of experience with timing constraints, STA methodologies, and timing closure at both the block and full-chip levels.
• 5+ years of experience with synthesis, place-and-route, and parasitic extraction flows.
• 5+ years of experience applying advanced timing concepts for leading-edge semiconductor technologies (5nm or below), including OCV, POCV, and PVT analysis.
• 5+ years of experience performing multi-corner, multi-mode (MCMM) timing analysis.
• 5+ years of experience using industry-standard timing analysis tools such as Cadence Tempus and Synopsys PrimeTime.
• 5+ years of experience developing automation and scripting solutions using Tcl, Python, and/or Perl.
• 5+ years of experience collaborating with RTL Design, Architecture, Physical Design, and Full Chip teams to drive timing closure.
• Demonstrated ability to work independently with strong prioritization, problem-solving, and solution-oriented decision-making skills.

Nice To Haves

• Experience with advanced FPGA or high-performance ASIC designs.
• Experience developing timing methodologies and automation for large-scale hierarchical designs.
• Experience defining hierarchical timing budgets and driving interface timing closure.
• Experience generating and validating timing ECOs during implementation and sign-off.
• Familiarity with clock tree synthesis (CTS), clock planning, and clock architecture optimization.
• Strong understanding of digital design fundamentals and physical implementation methodologies.
• Excellent analytical, debugging, and root cause analysis skills.
• Strong written and verbal communication skills with the ability to collaborate across multidisciplinary engineering teams.

Responsibilities

• Drive timing closure at block level and sub-system level.
• Developing methodology through flow/scripting which will result in easier interface timing closure at full chip.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at lower nodes, including POCV and PVT effects.
• Provide actionable timing feedback at both block and sub-system levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Global clock planning for easier interface timing closure.
• Work closely with design, implementation, and full chip teams to drive timing convergence, providing sign-off level expertise and guidance.

Benefits

• The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
• We also offer incentive opportunities that reward employees based on individual and company performance.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior