Timing Design Engineer

Apple • Beaverton, OR

3h

About The Position

Apple is a place where individual imaginations come together, committed to values that foster great work. Every new product, service, or Apple Store experience is a result of strengthening each other's ideas. This is driven by a shared belief in creating wonderful things to share with the world, improving lives. The diversity of people and their thinking inspires innovation in everything Apple does, leading to the best work when everyone is included. As an ASIC STA Engineer, you will be responsible for all aspects of SoC design related to timing. This includes timing sign-off, developing STA and sign-off flows, and owning IP and block-level timing constraints for both regular and custom timing requirements from synthesis to sign-off, ensuring high-quality timing constraints. You will collaborate closely with RTL designers to understand design intent and clock structures, with CAD teams to develop flows, and with the Physical design team to achieve timing closure and sign-off. Additionally, you will devise methods to verify your timing constraints and innovate timing constraints and flows to facilitate timing closure and address any potential pessimism or timing analysis issues.

Requirements

• Bachelors of Science in Electrical Engineering
• Proven knowledge of the ASIC design timing closure flow and methodology
• 2+ years of experience in writing ASIC timing constraints and timing closure
• Expertise in STA tools (Primetime) and flow
• Knowledge of timing corners/modes, process variations and signal integrity related issues
• Hands on experience in timing/SDC constraints generation and management
• Proficient in scripting languages (Tcl and Perl)
• Strong communication skills

Nice To Haves

• Familiarity with synthesis, DFT and backend related methodology and tools
• Self-starter and highly motivated to be successful at Apple

Responsibilities

• Timing sign-off
• STA and sign-off flow development
• Ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints
• Closely interact with RTL designer to understand design intent and clock structure
• Interact with CAD to understand and develop flow
• Interact with Physical design team to close and sign-off timing
• Come up with ideas and plans to verify your own timing constraints
• Innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees