Timing Design Engineer

Apple • Cupertino, CA

5h

About The Position

Apple is seeking an ASIC STA Engineer to take on responsibilities spanning all aspects of SoC design in terms of timing. This role involves timing sign-off, STA and sign-off flow development, and ownership of IP and block level timing constraints from synthesis to sign-off to ensure high-quality timing constraints. The engineer will collaborate closely with RTL designers to understand design intent and clock structure, with CAD teams for flow development, and with the Physical design team for timing closure and sign-off. The position also requires developing ideas and plans for verifying timing constraints and innovating timing constraints and flows to facilitate timing closure and address potential pessimism or fallouts in timing analysis.

Requirements

• Bachelors of Science in Electrical Engineering
• Proven knowledge of the ASIC design timing closure flow and methodology
• 2+ years of experience in writing ASIC timing constraints and timing closure
• Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues
• Hands on experience in timing/SDC constraints generation and management
• Proficient in scripting languages (Tcl and Perl)
• Familiarity with synthesis, DFT and backend related methodology and tools
• Strong communication skills are a pre-requisite
• Self-starter and highly motivated to be successful at Apple

Responsibilities

• Timing sign-off
• STA and sign-off flow development
• Ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints
• Closely interact with RTL designer to understand design intent and clock structure
• Interact with CAD to understand and develop flow
• Interact with Physical design team to close and sign-off timing
• Come up with ideas and plans to verify your own timing constraints
• Innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis

What This Job Offers

• Career Level: Mid Level