Testing Engineer IV - PCIe

Astreya•San Jose, CA

About The Position

We are seeking an experienced and highly technical Hardware Verification & Validation Engineer to drive the end-to-end testing of our cutting-edge ASIC designs. In this dynamic role, you will bridge the gap between pre-silicon verification and post-silicon lab validation. You will architect robust UVM testbenches for next-generation PCIe interfaces and lead hands-on silicon bring-up in the lab. If you have deep expertise in high-speed IO and thrive in cross-functional debugging environments, we want you on our team.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a closely related technical field.
6–8+ years of hands-on, proven experience in ASIC development, pre-silicon verification, or post-silicon system validation.
In-depth, structural knowledge of all PCIe protocol layers (Physical, Data Link, and Transaction).
Strong coding proficiency in Python, C/C++, and SystemVerilog.
Solid familiarity with Linux environments and standard hardware debugging tools (e.g., JTAG, GDB, Trace32).

Responsibilities

Architect and execute comprehensive verification plans for PCIe Switch, Root Complex, and Endpoint configurations.
Build and scale UVM-based environments from scratch to rigorously test complex PCIe protocol behaviors, including LTSSM transitions and link training.
Leverage advanced simulation and emulation platforms to ensure high-performance throughput and strict protocol compliance across PCIe Gen 4, Gen 5, and Gen 6.
Partner closely with RTL design, architecture, and software teams to root-cause and rapidly resolve functional failures.
Lead the initial power-on, initialization, and functional testing of high-speed IO interfaces, with a specific focus on PCIe Gen 5/6.
Utilize high-end laboratory equipment—including oscilloscopes, Bit Error Rate Testers (BERTs), and protocol analyzers—to validate electrical and functional correctness.
Reproduce complex silicon bugs in a physical lab environment and perform deep root-cause analysis to remediate hardware issues.
Develop and maintain robust automation frameworks using Python or C++ to streamline large-scale validation workflows and data collection.

Benefits

Medical provided through UHC (PPO, HSA, Surest options) / Medical provided through Kaiser (HMO option only) for California employees only
Dental provided through UHC Nationwide
Vision provided by UHC
Flexible Spending Account for Health & Dependent Care
Pre-Tax Account for Commuter Benefit/Parking & Transit (location-specific)
Continuing Education and Professional Development via various integrated platforms, e.g. Udemy and Coursera
Corporate Wellness Program provided by Goomi Group
Employee Assistance Program
Wellness Days
401k Plan
Basic and Supplemental Life Insurance
Short Term & Long Term Disability
Critical Illness, Critical Hospital, and Voluntary Accident Insurance
Tuition Reimbursement (available 6 months after start date, capped)
Paid Time Off (accrued and prorated, maximum of 120 hours annually)
Paid Holidays
Any other statutory leaves, paid time, or other ancillary benefits required under state and federal law