Technology Development Quality and Reliability Engineer

Intel•Hillsboro, OR

9d•Onsite

About The Position

The successful candidate will be working in Technology Development ESD, LU reliability engineering group focusing on research and development in Electrostatic Discharge (ESD) and Latch-up reliability area. This position is responsible for developing solutions and design rules to ensure ESD and latch-up reliability in circuits. The engineer will be responsible for but not limited to design test structures, run experiments, analyze data from test structures during technology development phase. ESD characterization on test structures using transmission line pulse (TLP) is required. Responsibilities also include develop, document, and publish design rules to aid internal and foundry design teams. Serve as a consultant to design teams to ensure ESD risks are addressed in analog circuits.

Requirements

Master's degree in Electrical Engineering, Reliability Engineering, Physics, or related technical field.
3+ years experiences in ESD or LU reliability engineering.
3+ years of experience with Device Physics, device characterization and/or basic VLSI design knowledge.

Nice To Haves

Ph.D. in electrical engineering and 1+ years of experience in ESD, LU reliability engineering.
Experience in planning and guiding the creation of test structure layout on test chips.
Experience in VLSI circuit design, including analog and digital.
Knowledge of state-of-the-art ESD circuit design techniques and topologies.
Deep understanding of transistor device characteristics and characterization methods.
Experience with transmission line pulse (TLP) measurement.
Experience on ESD models (i.e. CDM, HBM).
Data analysis background (JMP, Excel) to support design of experiments and analysis.

Responsibilities

Developing solutions and design rules to ensure ESD and latch-up reliability in circuits.
Designing test structures.
Running experiments.
Analyzing data from test structures during technology development phase.
Performing ESD characterization on test structures using transmission line pulse (TLP).
Developing, documenting, and publishing design rules to aid internal and foundry design teams.
Serving as a consultant to design teams to ensure ESD risks are addressed in analog circuits.