Technical Program Manager – GPU Floorplanning

NVIDIA•Us, CA

16h

About The Position

NVIDIA is seeking a highly capable Technical Program Manager (TPM) to partner closely with our GPU Floorplan team and multi-functional collaborators in driving the execution of large, complex, multi‑die SoC and chiplet programs. This role sits at the intersection of deep technical understanding and disciplined program execution. The TPM will work alongside floorplan, chiplet, architecture, PD, package, and design teams to ensure coherent planning, clear prioritization, and predictable delivery across fast‑moving and highly interdependent programs. The ideal candidate brings strong program management rigor and enough technical depth to understand early‑phase physical design and system‑level trade‑offs, enabling them to ask the right questions, surface risks early, and help the team stay focused on the highest‑impact work.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering or equivalent experience.
10+ years of relevant working experience.
Strong program or technical project management experience in complex hardware or silicon development programs.
Proven ability to manage highly interdependent, multi‑threaded execution across multiple partners.
Sufficient technical depth to understand and engage on topics such as SoC architecture, physical design flows, floorplanning, or chip integration (not hands‑on implementation, but informed judgment).
Excellent written and verbal communication skills, with the ability to synthesize complexity into clear status and decisions.

Nice To Haves

Prior experience supporting floorplan, physical design, chip integration, or early silicon planning teams.
Experience working on multi‑die, chiplet‑based, or large SoC programs.
Ability to operate effectively in environments with incomplete data, evolving requirements, and tight milestones.
Strong judgment in prioritization - knowing when to push, when to call out, and when to unblock quietly.

Responsibilities

Own and drive end‑to‑end execution tracking for large‑scale GPU / SoC floorplan programs across multiple dies and chiplets.
Build and maintain integrated program views spanning breakthroughs, dependencies, risks, and cross‑team interactions.
Ensure plans from multiple chiplet / die owners roll up into a cohesive, executable project‑level view.
Partner closely with floorplan and technical leads to identify, track, and prioritize critical technical issues impacting area, wiring, timing, and schedule.
Proactively identify execution risks, misalignment, and early warning signals across the program.
Drive structured risk reviews and mitigation planning, ensuring issues are visible early rather than discovered late.
Serve as a primary coordination point between floorplan and partner teams including architecture, RTL, PD, DFT, package, design, and tooling.
Improve the quality, consistency, and predictability of interactions across teams.
Help rationalize and mature program management processes as programs grow in size and complexity.
Champion better tooling, dashboards, and structured ways of working that reduce overhead on technical leads.