Technical Program Manager, Hardware Systems

Anthropic•San Francisco, CA

1d•$365,000 - $435,000•Hybrid

About The Position

Anthropic trains and serves frontier AI models on some of the largest accelerator fleets in the world, and we're now building the custom hardware systems that fleet will run on — from the package boundary out through boards, racks, interconnect, power, cooling, and the datacenter interface. We're looking for a Technical Program Manager to own execution of these hardware systems from concept through production deployment. You'll drive the program that turns architecture and specs into boards and racks that ship — managing ODMs, CMs, and component vendors on one side, and coordinating silicon, firmware, infrastructure software, supply chain, and datacenter teams on the other. This is a role on a new hardware team. You'll build the program cadence, review structure, and NPI process this team runs on. We need someone who has shipped hardware at scale, has a realistic view of ODM/CM schedules and where they break, and is comfortable owning consequential program calls without a large organization behind them.

Requirements

8+ years in hardware systems / NPI program management for compute, networking, storage, or accelerator platforms.
Direct ownership of at least one platform from concept through volume production — you can walk through its EVT/DVT/PVT arc, what broke, and how you recovered.
Working technical fluency across the hardware stack — power delivery, thermal, mechanical, high-speed interconnect, board design, system management — sufficient to interrogate status and push back credibly on architects and vendors.
Experience managing ODMs/CMs and component vendors, including SOW negotiation, build tracking, quality escapes, and escalation.
Track record of standing up program mechanisms on a new or early-stage hardware effort, not just operating inside a mature PLC.
Strong written communication — plans, reviews, and exec updates that many teams depend on.
Comfort operating with high autonomy and limited process in a fast-moving, ambiguous environment.

Nice To Haves

Experience with AI/ML accelerator systems (GPU, TPU, custom ASIC), HPC, or hyperscale datacenter platforms and their scale-up / scale-out fabrics.
Experience taking a first-generation, custom-silicon-based system from bring-up through fleet deployment.
Experience with liquid-cooled and/or high-density rack architectures, rack level high power distribution, or optical interconnect programs.
Familiarity with the chip-package-system interface and coordinating tightly with a silicon team.
Experience with datacenter integration, deployment, and fleet-scale reliability/RAS programs.
Practical experience using AI tools in your own workflow, and clear ideas about where they help and where they don't.
BS/MS in EE, CE, ME, or a related field, or equivalent experience.

Responsibilities

Own the integrated hardware systems program plan across board, chassis, rack, and interconnect — from requirements through EVT/DVT/PVT, qualification, and production ramp — and be the source of truth on schedule, risk, and readiness.
Drive execution with ODMs, contract manufacturers, and component/optics vendors: SOWs, build schedules, deliverable tracking, factory readiness, and escalation when they slip.
Stand up and run the NPI cadence — build matrix, engineering reviews, DFx, issue triage, exit criteria — and keep it lightweight enough that a small, senior team actually uses it.
Drive the bring-up and validation program for new platforms: lab and pilot-rack logistics, firmware/BMC/diagnostics coordination, test coverage, and the reliability and telemetry targets a platform has to hit before it enters the fleet.
Own the interfaces that make or break a hardware program: silicon (samples, package, power/thermal envelopes), datacenter (power, cooling, rack integration, deployment windows), infrastructure software (management plane, provisioning, telemetry), and supply chain (long-lead components, second-sourcing, allocation).
Run partner and technology evaluations as a program — candidate ODMs, reference platforms, connector/optics/memory options — and land build / buy / co-design recommendations with the architecture team.
Own program communication upward and outward — for an audience that ranges from architects to executives.
Develop and share AI-assisted approaches to hardware program management — issue-tracker synthesis, build-readiness checking, spec/BOM consistency, ODM-report digestion.