Technical Lead, Infrastructure Silicon Validation

Meta•Menlo Park, CA

1d•$212,000 - $294,000

About The Position

Meta's Infrastructure Silicon organization is seeking a Technical Lead for Silicon Validation to own and drive pre-silicon and post-silicon bring-up, validation, and qualification for custom silicon powering Meta's data center fleet. In this role, you will define the technical direction for validation methodologies, lead cross-functional efforts spanning design, architecture, and systems engineering, and ensure that Meta's infrastructure ASICs meet the highest standards of reliability, performance, and correctness before and after deployment at scale.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
12+ years of experience in ASIC pre- and post-silicon validation, including silicon bring-up, characterization, and productization for data center or high-performance computing applications
12+ years of experience with silicon debug, failure analysis, and root-cause methodologies across simulation, emulation, and physical silicon environments
Experience defining and leading organization-wide validation strategy, coverage planning, and test automation architecture for complex ASIC programs
Experience with Python, C, or C++ for developing validation frameworks, diagnostic tools, and test automation infrastructure
Experience collaborating across ASIC design, architecture, systems engineering, and external partners throughout the silicon development lifecycle

Nice To Haves

Experience with post-silicon bring-up, validation, and debug
Experience with RDMA, DPDK, or host driver development as it relates to silicon validation and performance characterization
Prior experience and expertise with networking and NIC products
Experience with high-speed interconnect and memory subsystem validation, including PCIe, Ethernet, DRAM (DDR4/5, HBM), or NVMe/Flash domains
Experience with data center systems management, bare-metal Linux environments, and fleet-scale silicon deployment and monitoring
Experience with emulation and FPGA-based platforms for pre-silicon test content development, coverage closure, and early bring-up enablement

Responsibilities

Own and lead pre-silicon and post-silicon bring-up, validation, and qualification activities across the full product lifecycle, from test planning and emulation through characterization and fleet deployment
Architect and drive development of scalable validation frameworks, diagnostic toolsets, and automation infrastructure targeting custom infrastructure ASICs
Lead root-cause analysis and resolution of complex silicon failures across pre-silicon simulation, emulation, and post-silicon environments, driving systematic debug methodologies across teams
Provide technical direction on validation coverage, test content prioritization, and silicon readiness criteria to ensure successful tape-out and productization milestones
Collaborate with ASIC design, architecture, and systems engineering teams to influence next-generation silicon design decisions based on validation findings and fleet production insights
Establish and enforce validation best practices, coverage metrics, and quality gates across the silicon development organization
Drive technical alignment across internal and external partners, including foundry, IP vendors, and platform teams, to resolve silicon-level issues and accelerate bring-up timelines
Mentor and provide technical guidance to other engineers across the validation organization, elevating team-wide capability in silicon debug, test automation, and characterization
Translate production fleet data and system-level use cases into actionable validation requirements and regression coverage improvements
Define long-term roadmaps for validation infrastructure and tooling to support Meta's growing portfolio of custom data center silicon