Technical Lead, Hardware/Software Codesign, TPU Inference

Google•Sunnyvale, CA

5d•$240,000 - $333,000

About The Position

As a Technical Lead on Google’s TPU Chip Architecture team, you will help shape AI/ML hardware acceleration by driving TPU technology for demanding AI/ML applications. The role bridges model architecture innovation and next-generation hardware design, defining the long-term strategic outlook and architectural roadmap for future machine learning training and serving capabilities. You will advocate integrating foundational ML research, including massive-scale frontier models, with custom silicon architectures to deliver high-performance, power-efficient accelerators. The position is part of Google’s AI and Infrastructure organization, which develops AI and infrastructure capabilities at scale for Google employees, Cloud customers, and users worldwide. The team works across software and hardware, including TPU development, Vertex AI, global networking, data center operations, and systems research.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
12 years of experience in computer architecture, chip architecture, or hardware-software co-design.
Experience developing systems for performance modeling, simulation, or system analysis.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience as a lead architect driving multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference.
Experience with deep learning frameworks such as PyTorch or TensorFlow and their underlying execution models.
Knowledge of semiconductor trajectories, including process, memory, interconnects, and packaging.
Understanding of ML trends, business drivers, and the software ecosystem.
Ability to engage and align stakeholders, hardware designers, and the global ML research community.

Responsibilities

Define and drive the technical roadmap and architecture for the hardware/software stack to deliver high performance for training and serving large ML models.
Serve as the technical liaison between advanced research, software, and hardware teams, guiding model architecture innovation to improve scaling, quality, and hardware efficiency.
Architect and oversee next-generation configurable simulation frameworks and cycle-accurate performance models for evaluating complex micro-architectural decisions.
Promote system-level performance analysis across distributed ML systems and develop methodologies to balance compute, memory bandwidth, and inter-chip network requirements.
Manage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence organizational strategy and transition concepts into production.