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About The Position
Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon for AI clusters. This role involves owning design execution on complex blocks within purpose-built products, focusing on cutting-edge PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies. It's a high-impact position in a hyper-growth company where you will collaborate with architecture, verification, DFT, and physical design teams to bring features from specification to silicon. You will also contribute to the design methodology that supports the company's roadmap. The ideal candidate will be passionate about shipping silicon that defines AI infrastructure.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of digital design experience, including at least one full chip from spec to tapeout
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
Nice To Haves
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
- Familiarity with formal verification, emulation, or assertion-based methodologies
- Background in advanced process nodes (7nm, 5nm, or below)
- Strong debug skills across pre-silicon and post-silicon environments
Responsibilities
- Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
- Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
- Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
- Partner with architecture to translate specifications into implementation-ready microarchitecture
- Collaborate with verification on testplans, coverage closure, and bug triage
- Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
- Mentor junior engineers and contribute to design methodology, scripts, and best practices
- Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
- Drive structured, data-driven design decisions in support of aggressive tapeout schedules
Benefits
- Discretionary bonus
- Incentives
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
