Systems Solutions Architect

Cadence Design Systems • San Jose, CA

2d • $185,500 - $344,500

About The Position

Cadence’s SSG Central Applications Engineering team is seeking a Systems Solutions Architect and Technical Lead to define compute-centric solutions for Physical AI. The role focuses on defining SoC subsystems for AI applications using Cadence DSPs, CPUs, NPUs, and accelerators. The architect analyzes Edge AI and Physical AI application requirements and optimizes subsystems for power, performance, area, and software flexibility. They also define SoC integration and software runtime requirements covering boot and control, runtime data flows, security, and safety.

The position sets the technical vision and architecture for subsystems in partnership with hardware implementation, software engineering, and performance modeling teams. Using Cadence’s Silicon Solutions Group IP portfolio, the architect implements Physical AI, Computer Vision, and Audio algorithms in deployed systems.

Requirements

• 12+ years in a leading architectural or system engineering role, with a demonstrable history of architecting complex systems from concept through production.
• Proven track record designing integrated solutions in which hardware features explicitly support software mechanics, and vice versa.
• Experience collaborating with or leading performance modeling teams using SystemC, TLM, or custom cycle-accurate simulator infrastructures.
• Experience in Physical AI, including robotics or autonomous systems, delivering real-time imaging and/or radar (spatial awareness, tracking) and advanced audio processing.
• Strong written and verbal communication skills.
• Ability to travel up to 10% of the time, including internationally.

Responsibilities

• Define and own system architecture for new hardware subsystems—including compute, memory, interconnects, and interfaces—and the corresponding software stack, including drivers, HAL, compiler runtimes, and middleware.
• Architect solutions using Cadence SSG IP, including Tensilica DSPs and CPUs, Neo NPU and application-specific accelerators, interface IP, and memory controllers.
• Partner with performance modeling teams to build cycle-accurate or transaction-level (TLM) SoC subsystem simulations and use simulation data to identify bottlenecks before silicon commitment.
• Provide architectural specifications to RTL/hardware implementation and software/firmware engineering teams, bridging the teams to ensure alignment.
• Serve as the final authority during system integration and validate that the software stack extracts maximum performance from the physical hardware features.
• Build scalable proof-of-concept and reference designs demonstrating the capabilities of the integrated Cadence IP platform.
• Serve as technical liaison with Cadence engineering partners and influence future IP roadmaps based on emerging Physical AI trends, such as robotics, autonomous systems, and edge transformers.

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental, and vision plan options
• May be eligible for incentive compensation, including bonus and equity

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed