System Verification Engineer

NVIDIA•Santa Clara, CA

1d•Onsite

About The Position

NVIDIA is a worldwide recognized division noted for groundbreaking technology, known for inventing the GPU in 1999, which accelerated PC gaming, redefined computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI. NVIDIA is a “learning machine” that constantly evolves by adapting to new adventurous opportunities. The company's life's work is to amplify human imagination and intelligence. This role is for a System Verification Engineer to join the Emulation division, working onsite from the Santa Clara, CA headquarters. NVIDIA is a world leader in accelerated computing, pioneering solutions for challenges no one else can solve, with work in AI and digital twins transforming industries and impacting society.

Requirements

M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field with 4+ years of proven experience.
Proficient in Verilog and/or VHDL, C/C++ and SystemVerilog.
Protocol knowledge of at least one of the High-speed interfaces: PCIe/CXL/NVLINK/IB/Ethernet etc.
Knowledge of Low-speed protocols like I2C/I3C/SPI/UART and BMC interaction in server platforms.
Experience with UVM verification environments and scripting with Perl, Python and C/C++ is essential.
Familiar with hierarchical design approach, top-down design, SoC and system level verification.

Nice To Haves

Working Knowledge of CPU - GPU coherency, Prefer ARM CHI coherency protocol
Zebu emulation experience with SOC/CPU

Responsibilities

Support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches).
Bring up GPUs, SOCs, Switch, NIC on emulation, root causing system level test fails and emulator environment issues.
Bring-up and verify High Speed protocols like PCIe/CXL/NVLINK/IB/Ethernet etc.
Bring-up/debug issues related to CPU and GPU Coherency for low speed protocols like I2C/I3C/SPI/UART.
Continually collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams.
Work constructively leading emulation vendors to debug issues using various tools.
Write monitors and checkers that aid debug in HW test issues and FW/SW bring-up.