System Validation Lead, Staff (AI Accelerator Platform)

Qualcomm•San Diego, CA

3d•$145,600 - $218,400

About The Position

Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases. This role focuses on content quality and system-level validation enablement, offering deep exposure to Qualcomm SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains. Excellent Opportunity to work on cutting-edge SoCs across multiple product segments, including: Premium mobile and flagship platforms, Data center, AI Accelerator platform. We are seeking a highly experienced system validation lead to drive validation strategy, test planning, content development, and execution for next-generation AI accelerator platform. This role owns end-to-end system-level validation content across emulation and silicon phases while partnering with Architecture, Design, DV, Software, Performance, Power, and Product teams to ensure comprehensive coverage and successful product execution. The ideal candidate combines strong SoC architecture knowledge, validation expertise, technical leadership, and program management skills to lead geographically distributed engineering teams and deliver high-quality validation solutions at scale.

Requirements

BS or MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
8+ years of experience in silicon validation, or platform bring-up.
Strong understanding of operating systems concepts, caching, virtual memory, and embedded software fundamentals.
Experience with bare-metal software development and low-level hardware interfaces.
Excellent problem-solving skills and the ability to work in a dynamic, collaborative environment.
Experience programming in C, Assembly language.
Some exposure to scripting language (Python, Linux shell, etc.).
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

Experience with developing and applying machine learning models for system validation.
Familiarity in reading and understand the RTL code (e.g. Verilog, VHDL) and use the knowledge in the context of silicon validation.

Responsibilities

Define, develop, and optimize validation tests for multi-processor systems with a focus on system level concurrency.
Develop and maintain bare-metal software, including low-level hardware interfaces, register and interrupt programming, and clock and power management.
Collaborate with hardware and software teams to define and validate system level software use cases.
Debug and troubleshoot System-On-Chip with limited visibility, using development boards and lab equipment.
Implement and optimize algorithms for performance, power efficiency, and memory footprint.
Support pre-silicon validation efforts, working with simulation, emulation, and FPGAs.
Conduct post-silicon bring-up, validation, system level use cases, and system integration.