System Validation Engineer

ALTEN Technology USA•Foster City, CA

3d•$115,000 - $135,000•Onsite

About The Position

ALTEN Technology USA is seeking an experienced System Validation Engineer to join its System Validation (SVT) team in Foster City, California. The team owns system-level vehicle validation, confirming that fully integrated systems—including ECUs, subsystems, and software—behave as intended at the system boundary. This role focuses on behaviors that emerge through interactions among real subsystems, including cross-ECU timing, arbitration, fault propagation, and network load. The work supports reliability for Robotaxi Service Operations. The engineer owns validation for assigned System Technical Specification documents across domains such as Thermal, Steering, Braking, Lighting, Power Management, Network, and Charging. The role includes developing traceable verification plans, defining system test configurations, building and commissioning benches, performing integration and regression testing on benches and vehicles, supporting automation, analyzing defects, and providing release-readiness sign-off and program reporting. The engineer also supports Vehicle Systems Integration-led SFMEA activities by helping ensure findings are reflected in system-level test coverage.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, Computer Engineering, or equivalent.
At least 5 years of experience in vehicle system validation, system integration, or systems engineering roles.
Proven experience validating integrated multi-ECU systems against system-level requirements in one or more vehicle domains.
Deep technical understanding of automotive communication protocols (CAN, LIN, Ethernet), network topologies, and 12V power management.
Hands-on system-level testing experience, including instrumentation, restbus simulation, fault injection, and advanced data analysis.
Experience developing system test plans (DVPs) with requirements traceability in tools such as Polarion or IBM DOORS, informed by SFMEA analysis.
Working knowledge of System Failure Mode and Effects Analysis (SFMEA), including translating failure modes, effects, and mitigations into system-level test coverage.
Excellent written and verbal communication skills and ability to explain complex technical concepts to multidisciplinary teams.

Nice To Haves

Experience designing HIL or system test benches, including rapid prototyping tools such as dSpace and xIL environments.
Experience with CI-integrated test infrastructure and test automation at scale.
Experience with automotive diagnostics (UDS) and vehicle bring-up.
Experience with ISO 26262 functional safety.
Experience taking a vehicle program from prototype to launch.
Experience with structured problem-solving methodologies such as Six Sigma, Shainin RedX, and 5 Why.
Scripting and test automation skills; Python preferred.

Responsibilities

Own system-level validation for assigned System Technical Specification (STS) documents and ensure every requirement has a defined verification method and test coverage.
Create and maintain Design Verification Plans (DVPs) for system domains with full requirement-to-test-case traceability.
Define system-level test configurations from system boundary diagrams, using real ECUs and restbus-simulated peers in parallel, tree, or other topologies.
Design, build, and commission system test benches; coordinate with Vehicle Systems, Hardware, and Firmware teams on bench readiness and boundaries between bench, SIL, and vehicle testing.
Execute multi-ECU and cross-domain integration, functional, and regression testing on benches and vehicle assets under nominal and off-nominal conditions; analyze data and produce actionable insights.
Support test automation and infrastructure planning so system DVP regression coverage scales across vehicle platforms.
Drive system-level defect triage and root cause analysis, track issues to resolution, and retest after fixes.
Support VSI-led SFMEA activities by reviewing failure modes and mitigations, providing input on testability and detection, and ensuring findings are covered by system-level tests.
Provide system-level release-readiness sign-off against program gate exit criteria and report coverage, risks, and mitigation plans in program reviews.