System Performance Modeling Engineer

Qualcomm•San Diego, CA

3d•$115,600 - $173,400

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The Infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of platform infrastructure HW components such as Interconnect (NoC), System Cache, Memory Controllers and System MMU that are implemented in all Qualcomm SoCs. This position is centered on system/platform architecture, with a strong emphasis on NoC (Network-on-Chip) topology architecture and system memory architecture (topologies, memory organization, address mapping, interleaving, etc.). It involves architecture-oriented performance explorations using cycle-accurate and approximate models to support both Infra IP-level micro-architecture optimizations and system-level architecture decisions. Power modeling is also a key component of this job. The ideal candidate should demonstrate the ability to understand the HW micro-architecture of the infrastructure components involved — in particular the NoC, memory system, and overall platform interconnect — identify architectural trade-offs and performance bottlenecks, define experiments, and conduct data-driven performance and power analyses using simulation. The candidate should partner effectively with IP designers, system architects, and performance teams to shape next-generation platform architectures. This is a challenging position, working on the most innovative technologies, surrounded by experts as well as users of our technology all over the world. You will contribute to evaluating and shaping the architecture of future hardware platforms and provide key data points to decision-makers. You will also help develop new tools for architecture validation and exploration, primarily for performance and power, and to a lesser extent for high-level functional validation.

Requirements

Robust understanding of computer architecture, memory hierarchy, and system/platform architecture.
Experience or knowledge in NoC (Network-on-Chip) architecture, topologies, and design trade-offs.
Strong knowledge of Object-Oriented Programming (C++, Python).
Interest in programming paradigms.
Knowledge of bus components and interconnect micro-architecture.
Understanding of performance/power/area trade-offs.
Ability to quickly react and adapt to changes.
Excellent communication skills.
Degree in Microelectronics, Computer Science, or related field.
Preferably 2–5 years of solid experience in SoC modeling and/or software development; new graduates will be considered with strong internships & motivation.
Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite and NoC concepts and topologies.
Experience in Data Science, Machine Learning.

Nice To Haves

Master's or PhD degree in Microelectronics, Computer Science, or related field.
Strong mathematical background.
Knowledge of NoC architecture and network traffic engineering.
Knowledge of Memory Controller, LPDDR & DDR protocols.
Experience driving architecture-oriented performance and power investigations on blocks like NoC, memory controller, system cache, CPU, GPU, and multimedia is a plus.

Responsibilities

Participate in NoC topology and system memory architecture exploration campaigns, working closely with key architects from various teams. Analyze complex datasets to identify insights and patterns that will help define the requirements for next-generation SoCs.
Drive architecture-oriented performance and power explorations across platform-level components (NoC, memory subsystem, system cache, memory controllers).
Develop new tools for architecture validation and exploration — focused primarily on performance and power modeling, with additional support for high-level functional validation.
Support exploratory methodology projects, involving machine learning, data science, etc.
Expand, maintain, and document innovative modeling frameworks. Participate in defining a new hardware modeling semantic, breaking with conventional hardware programming languages.