System Hardware Board Design Engineering Leader (PCB) (Onsite)

Cisco•Milpitas, CA

1d•$194,600 - $285,700•Onsite

About The Position

The Common Hardware Group (CHG) at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products. This role is within the Cisco Service Provider Routing Hardware Engineering team, which develops next-generation hardware by adhering to IEEE standards and industry best practices. Engineers in this team drive innovation across the full product lifecycle, serving as IP architects, creators, and solution integrators. They design a new class of high-performance routers for the Internet of the future: Cisco 8000 Series routers. These cloud-enhanced systems are powered by Cisco Silicon One ASICs and deliver the scale, performance, and efficiency required by critical infrastructure. The engineer will collaborate with board design, ASIC, signal integrity, power, software, mechanical, thermal, manufacturing, systems, and supplier teams to define, design, validate, and release high-performance networking products.

Requirements

Bachelor’s degree in Electrical Engineering or Computer Engineering and 11+ years of experience, or Master’s in Electrical Engineering or Computer Engineering and 7+ years of related experience, or PhD in Electrical Engineering or Computer Engineering and 4+ years of related experience.
Experience in hardware board design and system architecture—taking products from concept through production—for high-performance systems, including PCIe, Ethernet, DDR, SerDes, and advanced thermal/EMI management.
Experience with high-speed digital design, signal and power integrity, power distribution, and reliability testing, supported by hands-on use of Cadence design tools and advanced lab instrumentation (oscilloscopes, logic/spectrum analyzers).
Experience leading complex, multi-site, and cross-functional engineering initiatives, partnering with silicon vendors and contract manufacturers to solve high-impact, ambiguous technical challenges at scale.

Nice To Haves

Experience with advanced networking systems, ASICs, FPGAs, high-speed memory, multi-gigabit SerDes, and advanced packaging.
Experience in co-packaged/near-packaged optics, signal/power integrity budget analysis, ultra-high-speed signaling, and next-generation power delivery.
Hands-on experience with Cadence (Concept/Allegro), HyperLynx, ANSYS, Keysight ADS, and advanced lab equipment (VNA, TDR, high-bandwidth oscilloscopes, protocol analyzers).
Experience with creating test scripts using Python to streamline validation and design tasks.
Analytical, methodical approach to decomposing complex issues, evaluating empirical evidence, and documenting clear, actionable conclusions.
History of working effectively within cross-functional teams to drive initiatives forward.
History of influencing senior technical and business leaders across organizational boundaries, underpinned by exceptional written, verbal, and executive-level communication skills.
Dedicated to driving excellence through the mentorship of senior engineering talent.
A record of delivering large-scale products and technical innovations, evidenced by a history of patents, influential publications, and active standards participation.
Committed to advancing the field through strategic thought leadership.
Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

Define long-term hardware architecture, power-delivery strategy, design standards, and technology roadmaps for high-performance networking systems.
Lead major, multi-disciplinary hardware initiatives from early concept through product release and customer delivery.
Act as a senior escalation point for novel or high-risk architectural, signal integrity, power integrity, reliability, field, and manufacturing issues.
Develop and communicate technical strategies that align multiple business units and engineering disciplines.
Establish reusable methods, constraints, verification practices, and quality standards for board design.
Guide senior engineers and technical leaders through architecture reviews, design tradeoffs, and complex investigations.
Represent hardware engineering in executive reviews, strategic supplier discussions, standards activities, and selected external technical engagements.
Anticipate industry and technology shifts and recommend investments in future hardware capabilities.
Drive decisions using simulations, laboratory evidence, product data, and a clear understanding of business impact.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (non-sales roles)
performance-based incentive pay on top of their base salary (sales roles)