Static Timing Analysis (STA) Engineer

Boeing•Tukwila, WA

4d•$146,200 - $239,200•Onsite

About The Position

The Boeing Company is seeking an experienced Static Timing Analysis (STA) Engineer to join their Boeing Electronic Products team in Tukwila, WA. This role is crucial for developing ASICs and FPGAs for Boeing's products. The team has experienced significant growth and offers opportunities to work on cutting-edge technology from research through flight insertion. Boeing values innovation, hard work, integrity, and achievement. The work supports customer missions by enabling connectivity, protection, exploration, and inspiration through complex SoCs and high-performance custom processors. The diverse development portfolio spans Space & Launch, AvionX, Missiles & Weapons, Strike, Surveillance and Mobility, and Autonomous Systems. As an STA Engineer, you will be responsible for pre-layout and post-layout timing for digital ICs/SoCs & FPGAs on critical Boeing Defense and Security programs. You will collaborate with electronics groups globally and a large physical design team to achieve timing convergence. This involves working with IP teams, EDA vendors, and Foundries for design closure.

Requirements

Ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
5+ years of experience with timing closure on ASICs and FPGAs
Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out.
Good understanding of RTL to GDS flow
Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
Ability to work with large physical design team to make the timing convergence successful

Nice To Haves

Lead, Level 5: 15+ years of related work experience or an equivalent combination of education and experience
10 or more years of experience with timing closure on ASICs and FPGAs
Completed multiple first-pass success ASIC tape-outs with intricacies (Cross clock domain, async crossing etc.)
Experience in using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)
Fair knowledge of Synopsys Fusion Compiler, Formality (Cadence LEC), and other relevant tools (e.g. TCM, Fishtail)
Synopsys physical design AI tool experience is a plus
Experience leading static timing closure and training new hires
Familiarity with space-based design techniques and radiation mitigation
Understanding of design for testability (DFT) and its implications on timing
Capable of working independently, self starter
Proficiency with multiple scripting languages (Python, C SHELL, TCL)
Capable of handling timing closure on multiple designs simultaneously

Responsibilities

Responsible for STA analysis and convergence throughout the ASIC cycle
Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
Facilitate STA methodology in collaboration with other STA leaders
Generate timing constraints for multiple ASICs and FPGAs
Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
Responsible for intricate cross domain timing path closure
Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
Programming skills with Python, TCL, Perl, Unix shell etc.
Help train new engineers