Staff Software Engineer

Intuitive•Detroit, MI

16d•$190,300 - $322,100•Onsite

About The Position

As a Staff Software Engineer reporting to the Managing Staff Software Engineer in the MP Platform Engineering group, you will be the technical leader responsible for the architecture and implementation of mixed-criticality embedded virtualization. You’ll define how a next-generation surgical robotic system safely consolidates critical/real-time and non-critical software onto shared hardware. You will own the key elements of the virtualization safety strategy: partitioning architecture, hypervisor configuration, silicon and platform software tuning for freedom from interference. Beyond virtualization, you will leverage your broad expertise and unique technical knowledge to contribute to company objectives, lead cross-functional projects from concept through completion, and coach colleagues in advancing their technical expertise. You will take ownership of multiple aspects of the embedded platform, exercising independent judgment on ambiguous, high-impact problems and influencing senior stakeholders on technical direction and associated risk. In your first year, you will Ramp on the platform's hardware/software stack, safety requirements, and existing hypervisor deployments. Deliver an architecture recommendation for the hypervisor strategy, accounting for partitioning, determinism, and the safety implications of each hypervisor's certification posture. Characterize behavior on target hardware and produce the initial analysis artifacts demonstrating freedom from interference. Stand up the instrumentation needed to give the team visibility into timing, utilization, and VM/platform health.

Requirements

Demonstrated expertise in designing scalable, high-performance embedded software architectures; advanced proficiency in modern C++ and Python for real-time systems.
Experience building from 0 to 1: define, build, and evaluate technical prototypes that de-risk platform decisions early, translating open architectural questions into measurable experiments on target hardware.
Extensive experience in Linux/QNX environments, including kernel modules, resource managers, POSIX applications, and distributed inter-processor communication frameworks.
Proven expertise with FPGAs, hardware accelerators, PCIe transport/configuration/enumeration concepts, and network stacks; strong ability to root-cause interdependent hardware/software problems.
Proven track record of leading strategic technical initiatives from concept through completion; ability to work independently and drive results with limited supervision.
Exceptional communication skills with demonstrated ability to articulate complex technical concepts and influence senior leadership across organizational levels.
Strong leadership capabilities, including mentoring engineers at all levels, providing technical direction, and potentially supervising activities of others.
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related engineering discipline.
Minimum of 12 years of related experience with a Bachelor's degree; or 8 years with a Master's degree; or a PhD with 5 years of experience.

Nice To Haves

Experience with Xen internals (dom0/domU, PV/HVM/PVH, xl configuration, Xen on ARM or x86) or with hypervisor contributions upstream.
Experience with functional safety and regulatory standards such as ISO 26262, IEC 61508, DO-178C/DO-297, IEC 62304, ISO 14971, or IEC 60601, including partitioning and interference requirements.
Familiarity with Ethernet fundamentals & OSI layers, clear understanding of Time Sensitive Networking standards and features (802.1AS, Qbv etc.).
Familiarity with modern build and CI systems (Bazel, Nix, Jenkins) and with Python for automation, analysis, and test.

Responsibilities

Define the virtualization safety architecture for a mixed-criticality system, ensuring spatial and temporal isolation between safety-critical and non-safety-critical applications.
Prototype and evaluate Xen and QNX hypervisors, defining an architecture based on safety, determinism, certifiability, and platform fit.
Own hypervisor system configuration and integration, implementing creative solutions to overcome platform limitations and gaps in vendor support.
Architect and implement deterministic inter-VM communication and device virtualization using virtio, shared memory, and PCIe/other device passthrough.
Plan and execute the analysis and verification needed to demonstrate freedom from interference, deterministic timing, and safe failure behavior in a regulated environment.
Lead failure modes and effects analysis for the virtualized platform, translating identified failures and technology limitations into design mitigations, fault containment, and defined recovery or degraded behaviors.
Build platform observability that exposes guest and hypervisor health, resource utilization, latency, jitter, and other relevant system health signals on target hardware