Staff SOC Mixed Signal Engineer

Qualcomm•San Diego, CA

4d•$155,168 - $210,000

About The Position

This individual leads, plans, PD implementation of ambiguous or conflicting requirements and performs the complex responsibility of the use of tools/applications (i.e., Cadence Innovus, Synopsis PTSI, etc.) to execute advanced architecture and implementation of design in the physical design environment of multiple complex blocks and makes suggestions for design improvements with respect to timing, power analysis and physical verification. Develops an implementation strategy that meets system requirements and customer needs for team. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex implementation challenges, design, or verification problems. Owns the design and verification strategies of ASICs, and IP cores, reviews the strategies of more junior team members, and develops strategies for multiple IPs. Reviews complex IP execution results from more junior team members and completes own runs through the complete flow to ensure that challenges/violations are fully understood and analyzed. Develops and implements IPs using state-of-the-art tools (from Cadence, Synopsys, etc.) and deep sub-micron technology nodes (4nm, 3nm). Works with digital designer to understand and debug timing specifications, facilitate logic changes to improve clock frequency. Optimizes the clock latencies for major clocks to reduce the design ECO cycle time. Deep analysis of clock and data path timing to identify key issues. Runs advanced power checks on multiple blocks to ensure design specifications are met; makes recommendations to leadership when specifications are not met. Interprets the results of highly complex performance checks and reports them to team lead. Stays up to date on technical literature and technological advances and suggests areas for innovation. Writes, reviews, and edits own technical document in accordance with template and reviews and provides feedback on more junior engineers' documentation. Maintains regular communication with key team members to ensure continued alignment between team deliverables and product execution plan. Writes technical documentation and provides technical expertise for design or project reviews and project meetings to ensure team's best interest is represented. Acts as a tech lead on small to large projects and owns team deliverables of the project. Continually evaluates process used in team to facilitate effective work-flow for possible improvement. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

Requirements

Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
Two (2) years of experience in a related occupation.
Experience with tools/applications such as Cadence Innovus, Synopsis PTSI.
Experience with advanced architecture and implementation of design in the physical design environment.
Experience with timing, power analysis, and physical verification.
Experience with ASIC engineering practices.
Experience with design and verification strategies of ASICs and IP cores.
Experience with deep sub-micron technology nodes (4nm, 3nm).
Experience working with digital designers to understand and debug timing specifications.
Experience with clock and data path timing analysis.
Experience with advanced power checks.
Experience writing, reviewing, and editing technical documents.
Experience maintaining communication with key team members.
Experience providing technical documentation and expertise for design or project reviews and meetings.
Experience acting as a tech lead on projects.
Experience evaluating process for improvement.

Responsibilities

Leads, plans, and implements designs with ambiguous or conflicting requirements.
Executes advanced architecture and implementation of designs in the physical design environment of multiple complex blocks using tools like Cadence Innovus and Synopsis PTSI.
Makes suggestions for design improvements regarding timing, power analysis, and physical verification.
Develops an implementation strategy that meets system requirements and customer needs.
Resolves complex implementation challenges, design, or verification problems using advanced problem-solving and ASIC engineering practices.
Owns the design and verification strategies of ASICs and IP cores.
Reviews the strategies of more junior team members and develops strategies for multiple IPs.
Reviews complex IP execution results from more junior team members and completes own runs through the complete flow.
Develops and implements IPs using state-of-the-art tools and deep sub-micron technology nodes (4nm, 3nm).
Works with digital designers to understand and debug timing specifications and facilitate logic changes.
Optimizes clock latencies for major clocks to reduce design ECO cycle time.
Performs deep analysis of clock and data path timing to identify key issues.
Runs advanced power checks on multiple blocks and makes recommendations when specifications are not met.
Interprets and reports the results of highly complex performance checks.
Stays up to date on technical literature and technological advances and suggests areas for innovation.
Writes, reviews, and edits technical documents.
Maintains regular communication with key team members to ensure alignment between team deliverables and product execution plan.
Provides technical documentation and expertise for design or project reviews and meetings.
Acts as a tech lead on small to large projects and owns team deliverables.
Evaluates team processes for possible improvement.
Acts as a strong contributor at design reviews and project meetings.
Communicates and implements a development plan.