Staff SoC Layout/EDA Designer

QorvoFort Lauderdale, FL

About The Position

As Staff Layout Designer, you will work as part of a cross-functional, global team delivering System-on-Chip (SoC) products from concept to high volume production for the consumer, industrial, and automotive industries.

Requirements

  • Minimum of Associate’s degree in Electronic Engineering or related field (Bachelor's degree preferred)
  • 5+ years relevant industry work experience required
  • Strong working skills with Cadence Virtuoso and PDK layout design tools (OA, CDL, GDS).
  • Strong working skills with physical verification tools (Pegasus/Calibre) and flows (DRC, LVS, ERC, PERC, LVL)
  • Detailed experience with analog/RF/mixed-signal layout in deep sub-micron, CMOS nodes (40nm and lower)
  • Understanding of LDE, ANT, ESD/LUP, NTN/TW/SOI isolation, matching, PnR parasitics, and EMIR concepts
  • Knowledge of digital physical design flows and techniques (VHDL, Verilog, LEF, DEF)
  • Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM clients

Responsibilities

  • Work with analog/RF/mixed-signal design engineers and digital engineers to create/optimize layouts of complex blocks and chip-level SoC macros
  • Work on continuous-improvement projects to automate/customize layout work flows through scripting and batch-mode operations
  • Produce high quality analog/RF/mixed-signal macros using industry best practices for layout and physical verification
  • Own block-level layout designs and top-level floor planning including full hierarchical verification/debug
  • Lead, document, and communicate layout design flows and reviews efficiently including the tape-out process and project database management/archive
  • Help manage/support layout contractors and mentor junior layout designers
  • Collaborate with global team engineers/designers to ensure designs are specification compliant and on time
  • Work independently on complex tasks while staying in sync with team activities/plan
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