Staff RFIC Design Engineer

Western Digital • San Jose, CA

1d

About The Position

WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide. This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today. We’re looking for people who want to build, solve, and operate at that level. Join us and let’s shape the future of data.

Requirements

• Hands-on design and development experience in analog and mixed-signal integrated circuit.
• Experience in at least one preferably multiple area of full CMOS circuit design and development in: Amplifiers – operational, instrumentation, wide-bandwidth etc.
• PMIC – Linear and switched regulators, Low-drop out regulators etc.
• Data converters – ADC, DAC, Flash and SAR type.
• Experience in 40nm and below CMOS technology.
• Demonstrable track record of successful design releases and mass production.
• Thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.).
• Experience with analog layout techniques of mismatch reduction, gradient suppression, parasitic effects minimization.
• Experience with floor planning, block level routing and top level chip routing.
• Knowledge of high performance and deep CMOS analog reliability considerations such as EM-IR, SOA and VDR and relevant mitigation techniques.
• Functional knowledge of logic digital circuits and understanding of basic digital design flow.
• Strong written and verbal communication skills.
• BSEE with minimum 10+ years of experience OR MSEE with minimum 8+ years of experience OR PhD with minimum 4+ years of experience.

Nice To Haves

• Experience working with distributed design teams a plus.

Responsibilities

• Design of high performance analog and mixed-signal circuit blocks.
• Transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation.
• Ability to communicate at all levels and with cross functional groups.
• Demonstrated track record of circuit innovation.
• Be a team player, be adaptable, and accept constructive criticism.

Benefits

• Paid vacation time
• Paid sick leave
• Medical/dental/vision insurance
• Life, accident and disability insurance
• Tax-advantaged flexible spending and health savings accounts
• Employee assistance program
• Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
• Tuition reimbursement
• Transit
• The Applause Program
• Employee stock purchase plan
• WD Savings 401(k) Plan

What This Job Offers

• Job Type: Full-time
• Career Level: Senior