Staff Research Scientist, AI-Hardware Co-Design

Analog Devices•Boston, MA

1d•Onsite

About The Position

The Algorithmic Solutions Group develops cutting-edge, efficient algorithms to bring intelligence to the physical world. We fuse state-of-the-art machine learning with deep domain expertise to convert raw physical data into actionable insights, solving the hard problems where off-the-shelf solutions fall short. We are seeking a Staff Research Scientist, AI-Hardware Co-Design to architect the solutions that power the next generation of intelligent systems. Through rigorous analysis and proof-of-concepts, you will bridge the gap between advanced AI algorithms and hardware implementation to define the optimal compute strategy. Operating at the boundary of software and silicon, you will drive the co-design of algorithms and architecture, defining the computational foundation to enable physical intelligence.

Requirements

PhD specialized in Computer Architecture or Integrated Circuit Design for AI workloads, and have 3+ years of industry experience applying architectural principles to real-world engineering constraints.
Profound understanding of how to organize computation and data. Demonstrated by either leading the design of complex AI SoCs, or by validating novel architectures through rigorous, cycle-accurate simulation. Operate at the structural level of the machine, optimizing memory hierarchies, on-chip networks, and execution models to solve complex data movement and efficiency challenges.
Deep expertise in hardware-aware deep learning. Proficient in modern frameworks (PyTorch, JAX) and capable of training or fine-tuning models to validate architectural hypotheses. Master the optimal mapping of computational graphs to silicon, orchestrating dataflow, tiling, and quantization (INT8, mixed-precision) to maximize arithmetic intensity within strict edge power budgets.
Navigate the ambiguity of early-stage innovation with creative persistence, translating open challenges into concrete technical roadmaps. Excel at decision-making under uncertainty, justifying how your architectural trade-offs directly address the problem and create value.

Nice To Haves

Successfully taped out a complex SoC or a custom AI accelerator. Understand the harsh reality of physical design—from timing closure to power delivery—and how these downstream constraints influence early-stage architectural decisions.
Comfortable discussing Fourier transforms, noise floors, and sampling rates. Understand the intersection of classical Digital Signal Processing (DSP) and deep learning, capable of architecting systems where neural networks and traditional signal chains work in concert to extract information from noisy physical data.
Familiarity with Verilog/SystemVerilog or modern hardware construction languages (Chisel, PyMTL) is a strong plus, even if you will not be writing production RTL daily.
Strong publication record in top conferences and/or journals.

Responsibilities

Collaborate with business leads and domain experts to identify opportunities where intelligent systems—integrating sensing, actuation, and tightly coupled algorithms—can solve previously impossible problems. You will focus on challenges that require holistic system innovation rather than just off-the-shelf components.
Lead technical execution from architectural design to validated proof-of-concept. You will partner with researchers and hardware engineers to bridge the gap between abstract research ideas and deployable solutions.
Act as the "Physics of Compute" anchor for the research team. You will use high-fidelity simulation, modeling, and proof-of-concepts to quantify the impact of memory hierarchy, dataflow, and precision on system performance—distinguishing between viable product paths and impractical research concepts.
Drive the simultaneous optimization of algorithms and hardware. You will treat the algorithm and the compute engine as a unified design space, adapting neural architectures to exploit specific hardware capabilities while selecting the optimal compute substrate—from ultra-low-power MCUs to custom accelerators—to meet strict power and area constraints.
Maintain a deep awareness of the evolving AI hardware and algorithm landscape. You will bring the best ideas from the academic and industrial communities into ADI, mentoring junior engineers and guiding the team toward state-of-the-art compute paradigms.