Staff Physical Design Engineer

Marvell Technology•Irvine, CA

1d•$112,300 - $166,280

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, and networking applications.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree.
Progressive experience in back-end physical design and verification, including significant leadership roles
Experience in hierarchical physical design strategies, methodologies, and advanced process node challenges
Understanding of current design technologies used in major foundries
Understanding of ASIC design flow, RTL integration, synthesis, and timing closure highly preferred
Strong knowledge of modern EDA tools and flows
Preferred experience in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness
Strong communication and collaboration skills, with the ability to influence cross-functional teams and executive stakeholders
Experience in developing and deploying advanced physical design methodologies and flows

Nice To Haves

Knowledge preferred on static timing analysis (PrimeTime, Tempus), EM/IR-Drop/crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction (Quantus, StarRC), formal or physical verification (Formality, Verplex, Calibre, Hercules) a plus
Familiarity with AI/ML-driven optimization in physical design tools is a plus

Responsibilities

Participate the long-term vision for physical design capabilities and infrastructure in alignment with company-wide technology strategy
Perform RTL-to-GDSII implementation for multiple SoC programs, including synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS)
Ensure successful and timely tapeouts of complex, high-performance SoCs
Participate in fostering a culture of innovation, collaboration, and continuous improvement
Drive cross-functional collaboration with design teams to influence design decisions and ensure successful project execution
Navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams
Explore development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality