Staff Mask Design Engineer

Renesas Electronics•Chandler, AZ

11d•Onsite

About The Position

We are looking for an experienced Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed-Signal ICs for Automotive applications. The role involves defining, developing, and delivering high-quality, manufacturable IC layouts using industry-standard technologies and tools. The successful candidate will contribute at block and Chip top level, lead layout activities, collaborate closely with design and cross-functional teams, and ensure robust physical implementation that meets performance, reliability, and quality requirements. The purpose of this role is to deliver robust, high-quality physical layouts for complex analog and mixed-signal ICs, ensuring manufacturability, reliability, and on-time delivery, while contributing to layout methodology, team capability, and continuous improvement.

Requirements

Bachelor’s or Master’s degree in Electrical, Electronics, or Microelectronics Engineering.
8+ years of experience in Analog and Mixed-Signal IC layout design.
Proven experience delivering complex layouts at IP, block, and Chip Top level.
Strong expertise in analog layout techniques, including: Floorplanning and top-level integration, Device matching and symmetry, Parasitic management, Latch-up prevention and ESD protection.
Solid understanding of electronics, semiconductor physics, and fabrication processes.
Hands-on expertise with layout and verification tools, including: Cadence Virtuoso / Virtuoso XL (OA, PVS), Mentor Graphics Calibre (DRC, LVS, PEX, DFM), R3D and related parasitic extraction tools.
Experience with advanced CMOS BCD technologies.
Experience using Mixed-Signal-on-Top (MSoT) flows.
Ability to define and execute advanced floorplan strategies.
Strong team player, self-motivated, and results-oriented.
Ability to work independently and collaboratively in a multisite, multicultural environment.
Excellent verbal and written English communication skills.
Clear, concise communication and presentation skills.
Ability to propose innovative and pragmatic solutions.
Strong focus on quality, reliability, and on-time delivery.
Willingness to undertake occasional international travel if required.
Comfortable collaborating with cross-functional teams including design, test, program management, and quality.

Nice To Haves

Experience in automotive or safety-critical semiconductor products is highly desirable.

Responsibilities

Implementing physical layouts for Automotive Business Line products at IP, block, and/or Chip Top level.
Driving and delivering floorplanning activities for blocks and top-level designs.
Participating in power supply strategy definition and signal distribution between blocks.
Delivering analog and mixed-signal layout blocks and contributing to top-level floorplan strategy.
Applying state-of-the-art layout techniques for device matching, parasitic reduction, ESD protection, latch-up prevention, and yield optimization.
Executing and signing off physical verification flows, including DRC, LVS, ERC, DFM, and parasitic extraction (PEX).
Working according to Analog-on-Top and Mixed-Signal-on-Top layout methodologies.
Attending relevant project and design reviews, reporting progress, risks, and schedule impacts.
Collaborating closely with design, verification, CAD, and technology teams to minimize rework and resolve physical implementation issues.
Identifying root causes and proposing solutions for issues observed during first silicon or prototype evaluation.
Contributing to design-for-quality, ensuring layouts are verified, validated, and suitable for long-term reliability and zero-defect goals.
Leading layout team activities, including task planning, execution, and knowledge sharing.
Participating in and contributing to training activities, technical documentation, and layout guidelines.
Taking a proactive role in personal development, continuous learning, and methodology improvement.