Staff Hardware Engineer, Electrical Engineering Design, Google Cloud

Google•Sunnyvale, CA

17d•$188,000 - $274,000

About The Position

The Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power Google services. Its computational challenges are enabled by custom hardware designed and made in-house. As a hardware engineer, you will design and build systems at the heart of Google's computing infrastructure and follow them from concept through high-volume manufacturing. The work can shape the machinery used in Google's data centers and affect millions of Google users. Individual pay is determined by job-related skills, experience, and relevant education or training. The listed U.S. compensation is $188,000–$274,000 USD, plus a 20% bonus target, equity, and benefits.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
6 years of experience working on electrical engineering design.
3 years of experience in technical leadership.
Experience with Machine Learning (ML) and Artificial Intelligence (AI) hardware platforms, including Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs).

Nice To Haves

PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
8 years of experience working on board design, system architecture, and electrical engineering design.
Experience with data center engineering, AI/ML, server, storage, and networking products.
Experience solving system issues, driving technical innovation, and advancing a technical roadmap.
Ability to collect and organize details to reproduce results and explain findings.

Responsibilities

Drive end-to-end system architecture, technology roadmap, and board-level design for next-generation platforms, establishing technical direction and design standards across programs.
Lead multidisciplinary trade-off analyses across system, mechanical, thermal, and PCB layout teams to define high-density interconnect strategy, stackup architecture, and complex routing guidelines.
Architect power delivery networks (PDN) and high-speed signal pathways with SI/PI experts, establishing guidelines to ensure performance at hyperscale.
Oversee lab validation strategy, system bring-up, and root-cause analysis for critical architectural issues, and mentor engineering teams through complex debugging.
Lead cross-functional engineering initiatives with Silicon, Firmware, Software, Thermal, Mechanical, and Operations teams to deliver cohesive, scalable infrastructure solutions.
Influence manufacturing and vendor roadmaps to optimize Design for Manufacturing (DFM) and Design for Test (DFT) for high-volume, enterprise-grade deployments.