Staff Hardware Design Engineer, SoC/SIP

Qualcomm•San Diego, CA

15d•$134,800 - $202,200

About The Position

The Qualcomm Data Center AI Hardware Engineering team designs and develops motherboards/add in cards/modules for Qualcomm new AI System On Chip (SoC)/System In Package (SIP). Primary responsibilities include working with cross functional teams (mechanical, thermal, SI, PTE, regulatory, validation, manufacturing, etc.) for execution of projects from concept to production. Support rack level design and integration of cards, servers and networking switches. Join a world-class, multidisciplinary team that is shaping the future of AI infrastructure. You will be working alongside industry-leading experts across the entire AI infrastructure stack—from silicon, systems architecture, networking, and distributed computing to machine learning platforms and large-scale AI deployment. Our collaborative and fast-paced environment offers unparalleled opportunities for learning, innovation, and professional growth, empowering you to solve some of the most challenging problems in the industry.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
System/card/rack-level development, including architecture, design, validation, and deployment of enterprise-class hardware platforms.
Rack-Level Expertise: Proven experience in rack-level system integration, including chassis, backplane, cabling, airflow, and thermal management across multiple cards/modules.
Familiarity with rack-scale power delivery, including PDUs, VRMs, PMICs, and power budgeting across multiple boards.
Experience with rack-level diagnostics and bring-up, including debug of interconnects, signal integrity across long traces/cables, and system-level validation.
Understanding of rack-level mechanical constraints, EMI shielding, and compliance with data center deployment standards.
Collaboration with ODMs/OEMs on rack-level design and manufacturing, including review of mechanical drawings, thermal simulations, and compliance testing.
Board-Level Design: Deep knowledge of PCIe cards, motherboards, daughtercards, and backplane signal and power delivery.
Expertise in chassis design, airflow optimization, and thermal management.
Solid understanding of system software operation from bootloader to OS and application layers.
Component Qualification: Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory, and connectors for use in complex card and rack-level designs.
Design & Validation: Hands-on experience in dense, high-layer count PCB designs (8–20+ layers).
Skilled in PCIe add-in card/module design, debugging in high-performance systems (x86 and ARM).
Familiarity with JTAG tools for bring-up and debug.
Experience with networking switches and high speed ethernet interfaces
High-Speed Interfaces: Knowledge of high-speed serial I/O (6–10+ Gbps), PCIe Gen5/6, LPDDR4x/5x, DDR4/5, 200/400/800 GbE.
Experience with long PCB/cable topologies (0.35–1.5 meter), signal integrity, and compliance with current standards.
Ability to debug at packet/protocol level across link, transport, transaction, and command layers.
Memory & Clocking: Experience with LPDDR4x memory technologies, DIMM layout and validation.
Expertise in clock distribution, power distribution, SMBus, PMBus, SPI, PWM/Tach, and BMC integration.
Tools & Collaboration: Proficient in schematic capture and PCB layout tools (Cadence Allegro, Mentor Expedition).
Experience with circuit simulation tools (SPICE), signal/power integrity analysis.
Skilled in using lab equipment: oscilloscopes, logic analyzers, JTAG, SMBus, serial debuggers.
Strong collaboration with ODMs on joint designs, schematic/layout reviews, and compliance to Qualcomm design guidelines.
Firmware & Software: Good understanding of x86 FW/SW stack and firmware architecture.
Experience with BMC hardware/software integration and management.
Compliance & Testing: Familiarity with regulatory, environmental, and compliance testing for rack-level systems.

Nice To Haves

Master's Degree in Electrical and Electronic Engineering, Computer Engineering, or related field.
10+ years hardware engineering/Systems development experience or related work experience.
4+ years of experience with circuit design (e.g., digital, analog, RF).
4+ years of experience utilizing schematic capture and circuit simulation software.
4+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, debug tools, etc.

Responsibilities

Lead schematics design, PCB layouts, design reviews, component selections, mechanical and thermal designs, and develop test plans.
Co-develop functional specifications for systems, cards, sub-systems, and rack-level architectures.
Collaborate with internal teams and ODMs to develop and support customer-specific hardware and system requirements.
Facilitate consensus on technical trade-offs at hardware, software, and chip design levels.
Support architecture and card designs including accelerator SoCs, memory, I/O, power delivery, electrical/mechanical integration, and PCB definition/design.
Participate in the design and development of rack-level inference solutions, ensuring alignment with customer requirements and system-level performance goals.
Resolve architecture and design issues across system, card, and rack levels.
Assist in the bring-up and debugging of hardware systems, cards, and rack-level configurations.
Provide technical oversight of factory and manufacturing processes, ensuring quality and consistency across rack-level deployments.
Contribute to writing Statements of Work (SOWs) and ODM product requirements; drive technical milestones and deliverables.
Coordinate across multiple development sites, including Qualcomm locations and ODM/JDM partners in Taiwan and internationally.
Travel to development and customer sites as needed to support rack-level solution deployment and validation.
Influence and communicate technical recommendations across disciplines and geographic locations.
Coordinate and deliver technical training for ODMs, with a focus on rack-level system integration and deployment.