Staff GPU Design Verification Engineer – Formal Verification

Samsung Electronics•Austin, TX

1d•$151,000 - $226,600•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a Staff GPU Design Verification Engineer – Formal Verification, you will contribute to block and subsystem level formal verification for Samsung's next-generation mobile GPU. In this individual contributor role, you will execute formal verification in collaboration with architecture and RTL teams to ensure functional correctness, power gating mechanisms, and alignment with architectural intent. You bring solid expertise in formal methods and GPU or semiconductor design verification, with an interest in exploring new approaches as methodologies evolve.

Requirements

6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
5+ years of hands-on experience in GPU, CPU, or advanced semiconductor design verification with a focus in formal verification.
Solid understanding of computer architecture and graphics pipelines.
Strong programming and scripting skills in Python, Perl, C/C++, or equivalent.
Proficiency in SystemVerilog and SystemVerilog Assertions (SVA).
Working knowledge of formal verification methodologies, including property verification, data path checking, model checking, register verification, connectivity checking, and coverage analysis.
Hands-on experience with industry-standard formal verification EDA tools and methodologies.
Strong debugging, analytical, and problem-solving skills with the ability to propose and execute solutions independently.
Effective communication and collaboration skills, with the ability to work across RTL, architecture, and design teams in a fast-paced global environment.

Nice To Haves

Knowledge of memory subsystems or coherent interconnects.
Experience with constrained random verification using UVM (IEEE 1800 Universal Verification Methodology).
Exposure to developing or improving formal verification flows, methodologies, or tooling.
Exposure to low-power design techniques and verification of power intent (e.g., UPF concepts).
Interest in advancing the state of formal verification practices.

Responsibilities

Contribute to block-level formal verification strategy and execution by defining verification goals, properties, coverage objectives, and sign-off criteria for critical GPU features, including clock and power gating.
Architect and implement formal verification environments by collaborating with RTL and architecture teams to develop assertions, properties, and formal models using industry-standard formal tools and methodologies to validate complex graphics and compute behavior.
Ensure functional correctness by applying formal techniques to exhaustively verify corner cases, state-space behaviors, and safety properties that go beyond what simulation-based verification can achieve.
Contribute to debug analysis and root-cause resolution by analyzing formal failures, tracing counterexamples, and working closely with design and architecture teams to ensure verification aligns with architectural intent and improves design robustness.
Apply formal verification techniques including proof depth, bug hunting, complexity handling, bounded proof, failure triaging, cover scenarios, and convergence analysis to achieve formal verification closure on assigned GPU design features.
Exercise independent judgment in execution, methods, and evaluation criteria — breaking down complex verification problems into actionable tasks and delivering results with minimal guidance.
Contribute to project execution using Confluence, JIRA, and relevant planning techniques, and maintain documentation including formal verification test plans, convergence reports, and complexity analysis.
Participate in knowledge-sharing and foster a culture of ownership and engineering rigor within the team.