Staff FPGA Digital Engineer - 5

Northrop Grumman•Chandler, AZ

4d•$108,200 - $162,400•Onsite

About The Position

Northrop Grumman Space Systems is looking for a Staff FPGA design engineer to support the Electro-Optics (EO) Group within the Launch Vehicles business unit in Chandler, Arizona. As a Staff FPGA design engineer, you will apply advanced understanding and wide application of FPGA engineering principles, including mastery of methods and tools available for solving complex technical challenges. You will work closely with senior staff, junior staff, and cross-disciplinary teams (hardware, algorithms, and software) to provide technical solutions to a wide range of complex problems. The ideal candidate excels in fast-paced, collaborative environments and is comfortable managing multiple diverse assignments.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university and 12 years of relevant experience; or a Master’s degree and 10 years of experience; or a PhD and 8 years of experience.
Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application.
Advanced background in FPGA/SoC design, with mastery in complex firmware development using VHDL (preferred) or Verilog.
Extensive experience with AMD Xilinx FPGAs and SoCs, with proficiency in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets.
Advanced proficiency in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC)
Mastery with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
Strong experience creating and executing verification plans using simulation, analysis, and hardware bench testing.
Deep knowledge of Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred

Nice To Haves

MS or PhD in Electrical Engineering, Computer Engineering, or related discipline.
Active U.S. Government DoD Secret security clearance at the time of application.
Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications.
Prior experience with DoD missile defense programs and associated standards.
Direct experience with AMD Xilinx Versal Gen 2 or Gen 1
Mastery with both Vivado IDE and Vitis Unified IDE.
Advanced experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) with fabric-based controllers in FPGA designs.
Deep understanding of embedded C/C++ programming for integration with processors/SoCs.
Knowledge of high-speed PCB design and signal integrity.
Strong experience with OSVVM or UVM.

Responsibilities

Lead resolution of design and integration challenges, drawing on advanced technical knowledge and wide application across disciplines.
Develop and execute high-level test benches to verify FPGA designs for functional correctness and timing requirements, managing configuration of multiple FPGA bitstream builds.
Generate, verify, and integrate IO and image processing HDL modules, including functions definitions, HDL coding, module-level simulation, and integration with device architecture.
Ensure compliance with internal design standards throughout the development lifecycle and mentor less experienced engineers.
Prepare, present, and maintain comprehensive design documentation including schematics, simulation results, and verification reports.
Stay abreast of evolving FPGA technologies, tools, and industry methodologies, demonstrating mastery in methods and tools available for addressing technical issues.

Benefits

Relocation assistance may be available
health insurance coverage
life and disability insurance
savings plan
Company paid holidays and paid time off (PTO) for vacation and/or personal business.
overtime
shift differential
discretionary bonus
Annual bonuses
Long Term Incentives (for VP or Director positions)