AI Connectivity

Marvell Technology•Santa Clara, CA

16d•$111,070 - $166,400

About The Position

The Optical Digital Signal Processing (ODSP) PHY SW Team develops software for Marvell's DSP products used in pluggable optical modules—chips that form the backbone of the internet, moving data within and between data centers worldwide. Marvell is the market leader in direct-detect optical DSPs (100G to 1.6T), with products deployed in every major cloud data center and AI cluster. We own all SW components, including embedded FW, customer SDK, and lab scripts, and we're the go-to group for getting things done across the entire product lifecycle—from pre-silicon simulation through field deployment. The core responsibilities of the SW team include embedded FW running on our RISC-V-based multi-core MCU, a C SDK provided to customers, a Python-based GUI for in-field debugging, and test infrastructure for the above. The SW team is a key enabler for bringing a product to production, and the role of a Staff Engineer in our team is to ensure the overall success of that product. This role combines technical leadership with project coordination responsibilities.

Requirements

Experience in memory-constrained embedded C/C++ FW development
Architecture design & development, code reviews & testing, through to customer volume production
Understanding of embedded SoC, microcontroller architecture (RISC-V a plus), memory-mapped hardware interfaces, GPIOs, ISRs, etc.
Excellent verbal and written communication skills in English, and able to collaborate in a large cross-functional organization

Nice To Haves

Experience with SERDES, IM-DD/Coherent DSP, Ethernet/PCIe PHYs, and/or Optical Module SW
Experience with designing/developing/debugging software state machines, transitions, context saving, and error handling
Experience with mixed-signal (analog+digital) control and monitoring, PID/feedback loop control
Experience with bare-metal, RTOS, device drivers, Linux kernel, etc.
Familiarity with advanced compiler options and details (clang/gcc preferred)
Proficient in C and Python, with knowledge of git, Linux, makefiles, gdb, IDEs, bash
Familiarity with digital verification test flows, FPGA emulation, and hardware languages such as Verilog
Familiarity with lab equipment such as oscilloscopes, supplies, PNAs, ONTs
Understanding of Ethernet networking from the OSI model, with emphasis on the PHY up to the data link level
Familiarity with forward error correction, PCS framing, PMA/PMD, PRBS, and other PHY traffic schemes
Understanding of signal processing: histograms, BER, SNR, sampling phase, Shannon limit, impulse & frequency response, FFT, etc.

Responsibilities

Architecture, Design, Development, and Testing of embedded C firmware for controlling our extremely complicated DSP HW
Drive firmware development for DSP control blocks, including RX/TX signal processing, FEC, PLL/FLL, reference generation, and thermal monitoring
Technical reviews of firmware architecture, API design, and system integration approaches
Translate complex specifications from standards bodies (MSA/OIF/CMIS) or directly from customers into easy-to-digest requirements, and clear sequence diagrams to aid in development
Debug issues, drive to root causes with HW/Systems teams, and follow up with test/validation/customer support teams
Work with the cross-functional team to plan SW milestones, develop in sprints, close tickets, and roll out features for the product
Coordinate with Marketing, AE, Test, Validation, SW_QA, and Hardware teams to align on deliverables and schedules
Provide regular status updates on milestones, scope, dependencies, and blockers
Manage Agile sprint planning and backlog prioritization in collaboration with stakeholders
Technical discussions with tier-1 customers on feature requirements, API specifications, and implementation
Support customer bring-up activities and resolve field issues
Work with AE teams to understand customer expectations and deliver critical features
Handle customer-specific feature development such as FEC burst statistics, VDM telemetry, and CMIS compliance