Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer

Analog Devices•Wilmington, MA

1d•$131,285 - $190,108

About The Position

Analog Devices is seeking an experienced Staff Engineer to serve as a Digital ASIC Chip Architect and Signal Processing System Engineer. The role focuses on architecture and development of mixed-signal and software-defined radio (SDR) signal chains, including digital accelerators and subsystems. The successful candidate will develop system specifications from application requirements and contribute hands-on across the path from architecture to circuit implementation. The position works across development teams to specify and guide digital, firmware, software, and processor-subsystem requirements and architecture. It collaborates with analog, RF, firmware, and software teams and supports IC development programs from concept through tape-out and validation. The engineer will also mentor team members, help foster technical excellence and continuous learning, monitor emerging technologies, and engage customers, ecosystem partners, and ADI stakeholders in defining future SDR technologies. The position requires travel 10% of the time and is a first-shift/day-shift role. The expected wage range for a new hire is $131,285 to $190,108. Actual compensation may vary based on work location, experience, education, training, market data, pay equity, and other bona fide factors. The role qualifies for a discretionary performance-based bonus and includes medical, vision, and dental coverage, a 401(k), paid vacation, holidays, sick time, and other benefits.

Requirements

10 or more years of experience, including 5 years of digital IC design.
Expertise in digital signal processing, RTL design, and digital architecture.
Strong knowledge of firmware and embedded software.
Strong knowledge of radio architecture and signal chains.
Strong knowledge of microprocessor subsystems and digital accelerators.
Strong knowledge of DSP cores and custom compute architecture.
Strong knowledge of hardware/software co-design and digital modelling.

Nice To Haves

Experience with system-level modeling and simulation, such as MATLAB, SystemVerilog, or Python.
Signal-processing experience with radio signal chains.
Working understanding of signal processing for high-speed ADCs/DACs.
Experience with SerDes and high-speed interfaces.
Demonstrated ability in requirements capture and documentation.
Familiarity with SoC integration and verification methodologies.
Exposure to productization and manufacturing ICs in high-volume.
Strong written and verbal communication skills.

Responsibilities

Drive the definition and architecture of complex mixed-signal ICs and SDR chips, with a focus on digital accelerators and subsystems.
Collaborate with analog, RF, firmware, and software teams to support cohesive SoC and system-level design.
Capture and maintain stakeholder requirements and keep development teams aligned throughout the program.
Support IC development programs from concept through tape-out and validation.
Promote technical excellence and continuous learning, and mentor and engage team members.
Track industry trends and emerging technologies to guide architectural decisions and maintain competitive advantage.
Work with customers, ecosystem partners, and ADI stakeholders to define future SDR technologies.