Staff Engineer, Timing

Samsung Electronics•Austin, TX

1d•$151,000 - $226,600•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a Staff Timing (STA) Engineer, you will join the GPU Physical Design team to work on ensuring timing integrity and signoff readiness for Samsung’s next-generation GPU IPs used in premium smartphones and adjacent market segments. In this mid-level individual contributor role, you will collaborate closely with RTL, physical design, SoC integration, and EDA partners to develop and implement timing analysis and convergent strategies for complex GPU designs. You bring curiosity, hands-on STA expertise, a solid understanding of ASIC design flows, and a collaborative mindset to apply sound methodology and deliver high-quality timing closure and power recovery across functional and test modes. You execute hands-on timing analysis at top level, understand timing margin, generate and debug timing constraints for complex, multi-clock GPU IPs across functional and test scenarios. Contribute to improvement in model extraction, timing convergence, correlation, timing robustness, and power recovery. support cross-functional collaboration with RTL, physical design, and SoC teams to identify, debug, and resolve timing issues impacting block-level and full-chip closure, ensuring alignment between logical intent and physical implementation You Identify tool bugs and inefficiencies, influence flow and methodology enhancement, leverage industry-standard tools and exploring best practices—including OCV mitigation, low-power techniques, and ML-assisted exploration—to improve timing quality, convergence, and predictability. You support timing closure and signoff readiness by analyzing timing paths, providing feedback to floorplan, clocking and physical design, and applying timing budgeting, derating, and multi-voltage methodologies across advanced process nodes. You take initiative on moderate-to-complex projects, communicating openly and clearly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging GPU technologies

Requirements

6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
Working knowledge and experience with POCV, derating methodologies, and timing analysis.
Strong hands-on experience with industry-standard STA tools (e.g., PrimeTime, Tempus).
Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment.

Nice To Haves

Familiarity with advanced FinFET process nodes (5nm or smaller).
Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools.
Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure.

Responsibilities

Execute hands-on timing analysis at top level, understand timing margin, generate and debug timing constraints for complex, multi-clock GPU IPs across functional and test scenarios.
Contribute to improvement in model extraction, timing convergence, correlation, timing robustness, and power recovery.
Support cross-functional collaboration with RTL, physical design, and SoC teams to identify, debug, and resolve timing issues impacting block-level and full-chip closure, ensuring alignment between logical intent and physical implementation.
Identify tool bugs and inefficiencies, influence flow and methodology enhancement, leverage industry-standard tools and exploring best practices—including OCV mitigation, low-power techniques, and ML-assisted exploration—to improve timing quality, convergence, and predictability.
Support timing closure and signoff readiness by analyzing timing paths, providing feedback to floorplan, clocking and physical design, and applying timing budgeting, derating, and multi-voltage methodologies across advanced process nodes.
Take initiative on moderate-to-complex projects, communicating openly and clearly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging GPU technologies.