Staff Engineer, Serdes Analog Design

Samsung Semiconductor•San Jose, CA

6d•$157,000 - $243,000•Onsite

About The Position

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams. In this role, you will actively work on architecture and circuits of high-speed interconnect transceiver (Serdes). You will work on circuits for Serdes IPs, clock generation as well as traditional analog circuits. You’ll work with a team to develop high-performance and low-power serdes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet using cutting-edge process technologies.

Requirements

Bachelors with 10+ years, Masters with 8+ years or PhDs with 5+ years of experience.
Minimum 2+ yrs experience RF/Analog/Serdes SoC design experience.
Knowledge and experience with analog circuits/mixed signal circuits: such as bandgap, LDO, filters.
Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
Knowledge of Serdes architecture and high-speed interconnect standard (USB, PCIe, UCIe)
Well-versed in EDA tools (Cadence, Spectre, Totem, EMX)
Comfortable with scripting languages (Python, Matlab)

Nice To Haves

Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.

Responsibilities

Design low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologies
Translate component design specification to schematics.
Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.
Supervise layout designers to generate LVS/DRC clean layout.
Optimize layout to improve the power consumption and performance of circuits
Functionality and performance validation in Silicon