Staff Engineer, Program/Project Mgmt

Celestica International LP•Richardson, TX
•Onsite

About The Position

As the Staff Test Readiness Lead for HPS Test Engineering, you will own the end-to-end testing architecture, strategy, and execution for next-generation or products and infrastructure. This position bridges the gap between top-tier silicon designers, internal hardware/software teams, and volume manufacturing operations. You will be responsible for leading a high-performing team of test hardware and software engineers to develop comprehensive test solutions (ICT, FCT, SLT, BI and Boundary Scan). You will maintain critical cross-functional alignment with the Front-End Senior Manager, Back-End Senior Manager, and Director of Technology Roadmapping to maximize test coverage, minimize escape metrics, and optimize manufacturing throughput and first-pass yield.

Requirements

  • Six to twelve years in test engineering across structural and functional test, with real debug experience on early builds.
  • Able to discuss coverage with a designer and yield with a site manager.
  • Rack-level or tray-level specialisation depending on assignment.

Responsibilities

  • The single owner of test readiness for a programme, at rack or tray level.
  • Issues the MTRS, sets coverage, and signs that the product can be tested at yield before any build is authorised — proven by a measured result at EVT rather than a paper review months earlier.
  • Issue the MTRS with structural and functional coverage targets per insertion, before test development starts.
  • Agree the reduced-scope EVT test with design, software and the site, and report measured coverage and first pass yield at EVT exit.
  • Sign the Test Readiness Review before the Build Authorisation is issued.
  • Own test limits and guardband method with the design authority, and control the limit file against station-level edits.
  • Own golden unit designation and control, and the manufacturing diagnostics and provisioning package with Software.
  • Drive early-build debug to root cause within the agreed turnaround, and agree failure attribution at 8D closure.
  • Verify station correlation, Gage R&R and parametric data capture before the build.
  • Track NPI-phase DPPM, first pass yield and test time against budget for the programme.
  • Feed test escapes and coverage gaps back into the DFT rule set.
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