Staff Engineer, Physical Design/Implementation

Qualcomm • Toronto, ON

2d • CA$124,200 - CA$174,200

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. You will lead and drive physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes. This role requires strong technical leadership to synthesize ambiguous requirements, drive execution across cross-functional teams, and deliver high-quality silicon meeting aggressive power, performance, and area (PPA) targets. This is a replacement position.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor’s degree and 4+ years of progressive experience in ASIC Physical Design or related domain
• Strong experience with: End-to-end ASIC Physical Design flow
• Strong experience with: Timing closure and signoff methodologies
• Strong experience with: Physical verification flows
• Hands-on expertise in industry-standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
• Solid understanding of: Power delivery and reliability (IR/EM)
• Solid understanding of: Clocking architectures and CTS
• Solid understanding of: Large-scale SoC integration challenges
• Proven ability to lead complex PD execution in high-pressure tapeout environments
• Strong analytical and problem-solving skills with attention to detail
• Ability to synthesize ambiguous or conflicting requirements into execution plans
• Effective collaboration across global, cross-functional engineering teams
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

• Experience with high-speed SerDes / retimer designs (PAM4-class signaling)
• Experience with full-reticle or near-reticle SoC implementation
• Familiarity with multi-die / chiplet / advanced packaging architectures
• Exposure to data center, networking, or optical connectivity ASICs
• Strong scripting and automation skills (Python, Tcl)

Responsibilities

• Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including: Floorplanning, Clock Tree Synthesis (CTS), Placement & Routing, Power Delivery Network (PDN), Timing analysis and closure
• Plan and implement full-chip or hierarchical designs, including full-reticle-scale integration
• Drive timing closure across all corners and modes (MMMC), including SI-aware optimization
• Perform and review physical verification checks: DRC, LVS, Design-for-manufacturability (DFM), Design-for-yield (DFY)
• Collaborate with cross-functional engineering teams (front-end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
• Lead integration of high-speed SerDes macros and mixed-signal IP, ensuring robust floorplan and signal integrity alignment
• Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
• Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
• Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
• Develop and improve physical design methodologies and flows to enhance efficiency and scalability

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Senior