Staff Engineer, HIL Design, Hardware Integration & Test Automation

Cariad, Inc.•Mountain View, CA

6h•$161,710 - $234,325•Onsite

About The Position

We are CARIAD, an automotive software development team with the Volkswagen Group. Our mission is to make the automotive experience safer, more sustainable, more comfortable, more digital, and more fun. To achieve that we are building the leading tech stack for the automotive industry and creating a unified software platform for over 10 million new vehicles per year. We’re looking for talented, digital minds like you to help us create code that moves the world. Together with you, we’ll build outstanding digital experiences and products for all Volkswagen Group brands that will transform mobility. Join us as we shape the future of the car and everyone around it. Role Summary: The Staff Engineer, HIL Design, Hardware Integration & Test Automation is responsible for the hardware-oriented architecture, technical standards, and bring-up strategy for HIL benches, integration benches, harnesses, Interface Control Documents (ICDs), and lab automation used to validate CARIAD hardware platforms. This is a hands-on staff-level individual contributor role requiring deep experience in HIL design, embedded hardware, wire harnesses, system integration, and cross-functional technical leadership. The role defines scalable HIL architectures, reviews and approves harness and interface documentation, leads the most complex hardware bring-up and debug activities, and establishes repeatable test execution from requirements and ICDs through lab evidence. The Staff Engineer also owns the technical roadmap for the hardware side of an AI-enabled integration lab, including AI-agent-based workflows, MCP servers, equipment interfaces, automated evidence capture, governance, rollout metrics, and test orchestration for hardware validation.

Requirements

Staff-level technical leadership across HIL architecture, hardware integration, validation infrastructure, and lab automation.
Structured problem solving and disciplined hardware debug for ambiguous, cross-domain failures
Clear written, verbal, and executive-ready communication with data-backed recommendations.
Cross-functional influence across hardware, software, systems, validation, manufacturing, suppliers, and lab operations
Ownership of standards, documentation, issue tracking, action follow-through, risk escalation, and closure criteria
Ability to operate with urgency in a hands-on prototype lab environment while improving repeatability and safety
Ability to convert ambiguous lab problems into scalable processes, owners, evidence, and durable corrective actions
Process-oriented execution in complex, high-reliability systems programs with mentorship of less experienced engineers
Staff-level ownership of HIL architecture for embedded ECUs or comparable high-reliability systems, including architecture standards, signal/I_O mapping, fault insertion, load/sensor simulation, safety interlocks, and scalable bring-up methods.
Embedded hardware integration and bring-up across power, reset, clock, boot, peripherals, firmware, BSP, drivers, test infrastructure, and HW/SW issue isolation, with ability to guide other engineers through complex investigations.
Wire harness and ICD technical ownership, including connector/pinout definition, signal routing, shielding/grounding, continuity checks, electrical interfaces, protocols, timing, diagnostics, and coverage strategy.
Ability to interpret schematics, datasheets, PCB/connector documentation, debug reports, supplier deliverables, and system requirements to define coverage and resolve integration issues.
HIL bench and test fixture architecture/documentation, including benches, breakout/load boxes, fixtures, cable assemblies, configurations, readiness checklists, reuse strategy, and configuration control.
Strong lab instrumentation and interface knowledge, including scopes, meters, power supplies, loads, logic analyzers, CAN/Ethernet/serial tools, JTAG, CAN, LIN, Ethernet, USB, UART, SPI, I2C, GPIO, analog/digital I_O, power/wake lines, and diagnostics.
Python automation for instrument control, data capture, sequencing, log parsing, evidence collection, repeatable execution, and reusable automation libraries.
Structured debug and AI-enabled lab automation, including MCP servers/APIs or comparable interfaces for equipment control, orchestration, artifact retrieval, triage, governance, rollout metrics, and traceable closure.
Ability to define technical standards, mentor engineers, and influence lab practices across prototypes, harnesses, fixtures, benches, suppliers, and cross-functional engineering teams.
8+ years of relevant experience in HIL design, embedded hardware bring-up, wire harness/interface documentation, system integration, hardware validation, lab automation, or debugging of automotive or comparable high-reliability embedded platforms.
Bachelor's degree in Electrical Engineering, Computer Engineering, Systems Engineering, Mechatronics, or related technical discipline

Nice To Haves

Automotive ECU experience, including telematics, connectivity, infotainment, zonal controllers, high-performance compute platforms, or similar embedded hardware.
Commercial or custom HIL platform experience, such as dSPACE, NI/VeriStand, Vector, ETAS, Speedgoat, Keysight, or Python-based frameworks.
Experience with Linux, Android, QNX, Yocto, adb/serial console, flashing, bootloaders, diagnostics, manufacturing/EOL tooling, DV/PV, EMC/ENV, validation, or supplier issue support.
AI-agent lab workflow or AI roadmap experience, including setup checks, instrumentation control, failure clustering, evidence/report generation, tool interfaces, data architecture, governance, and measurable adoption.
Familiarity with systems, requirements, verification, safety, cybersecurity, or automotive process standards such as ISO/IEC/IEEE 15288/29148, IEEE 1012, ASPICE, ISO 26262, ISO/SAE 21434, DO-254, DO-178C, or SAE ARP4754A/B.
Master's degree in Electrical Engineering, Computer Engineering, Systems Engineering, Mechatronics, or related discipline

Responsibilities

Own staff-level HIL architecture for embedded automotive hardware platforms, including I/O strategy, signal conditioning, fault insertion, load/sensor simulation, safety interlocks, instrumentation, reuse patterns, and bench readiness criteria.
Define scalable bench architectures, configuration baselines, readiness checklists, and technical standards for HIL benches, integration benches, breakout/load boxes, fixtures, harnesses, and lab stations used for HW/SW integration and validation.
Lead the most complex board, ECU, and system bring-up across prototypes and revisions, including power, reset, clock, boot, flashing, communications, peripheral interfaces, diagnostics, and cross-domain issue isolation.
Provide technical direction for bring-up plans and debug strategies, ensuring ownership, evidence, decision records, and closure criteria are clear across engineering teams and suppliers.
Debug complex hardware/software interface issues using schematics, ICDs, harness drawings, logs, instruments, and controlled reproduction steps, while mentoring engineers on structured methods.
Own and approve harness drawings, pinouts, connector definitions, cable assemblies, and lab wiring documentation required for integration and HIL execution.
Serve as technical authority for Interface Control Documents (ICDs) for bench and system interfaces, including electrical definitions, signals, protocols, timing, diagnostics, power states, and test coverage mapping.
Translate requirements, ICDs, schematics, and supplier documentation into HIL coverage strategy, test procedures, hardware fixture needs, automation requirements, and validation evidence expectations.
Establish configuration control and release discipline for benches, harnesses, firmware/images, flashing steps, lab equipment, scripts, and test artifacts.
Support DV/PV, EMC/ENV, manufacturing, and end-of-line readiness by ensuring lab infrastructure can reproduce failures, validate corrective actions, and scale across program needs.
Own the hardware-side technical roadmap for an AI-enabled HW integration lab, including target workflows, tool interfaces, data sources, rollout plan, governance, safety constraints, and measurable execution benefits.
Define and guide implementation of MCP servers, APIs, or comparable tool interfaces for hardware testing, lab equipment control, bench state, test orchestration, artifact retrieval, and AI-agent operation.
Develop reusable AI-agent-based HW testing workflows for setup verification, instrumentation control, automated test execution, log capture, failure triage, evidence packaging, and status/report generation.
Partner with software, automation, IT, and validation teams to integrate AI agents with lab equipment, HIL frameworks, Jira, requirements repositories, SharePoint evidence, and test reporting tools.
Ensure AI-based lab workflows remain traceable, reviewable, safe for lab use, aligned with engineering judgment, and repeatable across programs.
Serve as staff-level escalation point for complex integration failures and drive structured triage across hardware, software, systems, validation, manufacturing, and supplier teams.
Influence supplier and internal deliverables for HIL equipment, harnesses, interface issues, board revisions, bench blockers, technical risks, and corrective actions.
Communicate status, blockers, risks, recovery plans, technical trade-offs, and decision needs with clear evidence and recommended next steps.
Document issues, debug findings, configurations, test evidence, technical decisions, and closure rationale in a structured and traceable manner.
Mentor engineers and improve lab practices, templates, checklists, and knowledge-sharing methods to strengthen repeatability and technical capability.